Abstract: In a music reproducing apparatus, a timbre data memory has a limited capacity for storing timbre data corresponding to a first number of timbres, which is less than a second number of timbres reserved in a data source. An interface can be operated to transfer the timbre data from the data source to the timbre data memory so that the timbre data memory stores the transferred timbre data. A score data memory stores score data representing a music piece. A tone generator is set with a tone generating parameter derived from the score data stored in the score data memory for generating tones of the music piece. A performance controller interprets the score data to read out timbre data designated by the score data from the timbre data memory for setting the tone generator with the read timbre data so that the tone generator can generate the tones having timbres specified by the score data.

Abstract: A power supply system has a judging circuit for judging occurrence of an overload condition by monitoring a power supply voltage applied to a device under test. The judging circuit detects, as reverse insertion of the device under test into a socket, occurrence of overload immediately after application of the power supply voltage to the device under test. Application of the power supply voltage to the device under test is shut down in a short time approximately equal to a rise time of the power supply voltage.

Abstract: A music playback device applicable to a portable telephone terminal device uses a sequence data FIFO memory and a waveform data FIFO memory both having limited storage capacities. A system CPU performs successive transfer of sequence data and waveform data in response to shortage events of the memories. Hence, it is possible to actualize high-quality playback of musical tunes with small storage capacities of the memories and with small load of processing of the system CPU.

Abstract: A music playback device applicable to a portable telephone terminal device uses a sequence data FIFO memory and a waveform data FIFO memory both having limited storage capacities. A system CPU performs successive transfer of sequence data and waveform data in response to shortage events of the memories. Hence, it is possible to actualize high-quality playback of musical tunes with small storage capacities of the memories and with small load of processing of the system CPU.

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK′ in a test mode. The ICLK′ signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK′ signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).