Abstract: A cathode ray tube controller holds a write-in address and displaying image data or a read-out address from a central processing unit. The cathode ray tube controller makes access to a memory by a write-in or read-out address from the central processing unit during a period in which the displaying image data in a horizontal scanning period are not read out from the memory, so that the read or write operation with respect to the memory can be carried out during the horizontal scanning period.

Abstract: A bit pattern conversion system for converting a sequence of a bit pattern between a central processing unit and a peripheral circuit, including a data bus line connected between the central processing unit and the peripheral circuit, and a conversion circuit provided in the peripheral circuit for converting the sequence of the bit pattern from a most significant bit to a least significant bit, and vice versa, in accordance with a conversion signal.

Abstract: A phase synchronization circuit for controlling a graphic display device in a teletext receiving system. The phase synchronization circuit includes a delay circuit, adapted to delay in sequence clock signals which are to be phase-synchronized with a reference signal and to produce in sequence delayed clock signals, and a selection circuit, including set/reset circuits and gates, each gate receiving the output of the set/reset circuits and of the delayed clock signals. Among the delay clock signals, the signal that has the nearest edge timing to the edge of external signals is selected. The phase synchronization circuit has a short pull-in time and high-speed synchronization, is suitable for circuit integration, and offers improved reliability.