Abstract: According to an embodiment, a circuit comprising includes a first switching circuit coupled to a power supply input, a second switching circuit coupled to an output of the first switching circuit, a supply capacitor coupled to the second switching circuit, and a startup cell coupled to the power supply input and the supply capacitor. The startup cell is configured to electrically couple the power supply input to the supply capacitor when the second switching circuit is not actively switching. The startup cell is also configured to electrically decouple the power supply input from the supply capacitor when the second switching circuit is actively switching.

Abstract: Methods, devices, and integrated circuits are disclosed for controlling switch timing in a power factor correction timing switch. In one example, a device is configured to receive one or more indications of one or more power factor correction circuit parameters. The device is further configured to determine a switch delay time based at least in part on the one or more power factor correction circuit parameters. The device is further configured to generate an indication of a switch on time for the power factor correction timing switch, wherein the switch on time is based at least in part on the switch delay time.

Abstract: According to an embodiment, a circuit comprising includes a first switching circuit coupled to a power supply input, a second switching circuit coupled to an output of the first switching circuit, a supply capacitor coupled to the second switching circuit, and a startup cell coupled to the power supply input and the supply capacitor. The startup cell is configured to electrically couple the power supply input to the supply capacitor when the second switching circuit is not actively switching. The startup cell is also configured to electrically decouple the power supply input from the supply capacitor when the second switching circuit is actively switching.

Abstract: Methods, devices, and integrated circuits are disclosed for controlling switch timing in a power factor correction timing switch. In one example, a device is configured to receive one or more indications of one or more power factor correction circuit parameters. The device is further configured to determine a switch delay time based at least in part on the one or more power factor correction circuit parameters. The device is further configured to generate an indication of a switch on time for the power factor correction timing switch, wherein the switch on time is based at least in part on the switch delay time.

Abstract: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication signal and the sync signal and an output interface for an oscillation signal synchronized with the external clock and having a duty cycle adjusted according to the duty cycle indication signal.

Abstract: Some embodiments of the invention include an integrated circuit having a node or pin to detect a first information during a first a detection period and to detect a second information during a second detection period. In some embodiments, the information at the pin may allow the integrated circuit to operate in a quasi-resonant operation. Other embodiments are described and claimed.

Abstract: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication signal and the sync signal and an output interface for an oscillation signal synchronized with the external clock and having a duty cycle adjusted according to the duty cycle indication signal.

Abstract: Some embodiments of the invention include an integrated circuit having a node or pin to detect a first information during a first a detection period and to detect a second information during a second detection period. In some embodiments, the information at the pin may allow the integrated circuit to operate in a quasi-resonant operation. Other embodiments are described and claimed.

Abstract: In a preferred embodiment, there is provided a switched mode power supply operable in start-up mode, normal mode and standby mode. The power supply may comprise a transformer having a primary winding on a primary side and a secondary winding on a secondary side, the primary winding being coupleable to a DC input voltage, and circuitry on the secondary side being arranged to provide a DC output voltage; and a power controller. The power controller may comprise a regulation controller for regulating a DC supply voltage on a supply line during standby mode, and a high voltage device coupled to the DC input voltage and the supply line. The current through the high voltage device to the supply line, during standby mode, may be controlled by the regulation controller. During standby mode, when the supply voltage is greater than or equal to a reference voltage, the current through the high voltage device to the supply line is substantially zero.