Patents by Inventor Junyi Sun

Junyi Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250071763
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first user equipment (UE) may receive, from a second UE, a first message that indicates a sidelink bandwidth part (BWP) switch, for the second UE, to a first sidelink BWP, where the first message includes an indication of the first sidelink BWP and a first sidelink resource pool in the first sidelink BWP. The first UE may transmit, to the second UE, a second message that confirms the sidelink BWP switch for the second UE. The first UE may receive, from the second UE, a third message that activates the sidelink BWP switch, for the second UE, to the first sidelink BWP. Numerous other aspects are described.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Inventors: Hua WANG, Sony AKKARAKARAN, Tao LUO, Junyi LI, Qing LI, Hong CHENG, Jelena DAMNJANOVIC, Peter GAAL, Juan MONTOJO, Yan ZHOU, Jing SUN, Jung Ho RYU
  • Patent number: 12237994
    Abstract: Various aspects of the disclosure relate to beam information for independent links. For example, beam information for one link may be sent on at least one other link. In some aspects, the independent links may involve a first device (e.g., a user equipment) communicating via different independent links with different devices (e.g., transmit receive points (TRPs) or sets of TRPs). For example, the first device may communicate with a second device (e.g., a TRP) via a first link and communicate with a third device (e.g., a TRP) via a second link. In some scenarios, one link can indicate beam switching for at least one other link. In some scenarios, one link can indicate link recovery for at least one other link. In some scenarios, one link can indicate link failure for at least one other link.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: February 25, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Tao Luo, Juan Montojo, Tamer Kadous, Junyi Li, Xiaoxia Zhang, Jing Sun, Taesang Yoo, Siddhartha Mallik
  • Publication number: 20250056431
    Abstract: This disclosure provides systems, methods, and apparatuses, including computer programs encoded on computer storage media, for wireless communication. Various aspects relate to initial physical random access channel (PRACH) power control using multiple PRACH signals, and more particularly to supporting one or more initialization and power control operations between a user equipment (UE) and a network entity prior to an association process. The initial PRACH power control may include the UE transmitting, to the network entity, a first set of PRACH signals at different respective power levels. The network entity may transmit a response message indicating a single set of PRACH signals detected by the network entity, and the UE may detect whether a first PRACH signal, of the first set of PRACH signals, is included in the single set of PRACH signals to select a power level associated with the first PRACH signal for transmitting association messages.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Inventors: Jing Sun, Xiaoxia Zhang, Jing Jiang, Junyi Li, Raviteja Patchava, Vamsi Krishna Amalladinne
  • Patent number: 12212445
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive first control signaling identifying a demodulation reference signal (DMRS) pattern that may be uniformly distributed in a time domain and a frequency domain. The DMRS pattern may include a first set of resource elements for the DMRS, a second set of resource elements for guard tones adjacent to and greater in frequency than the first set of resource elements, and a third set of resource elements for guard tones adjacent to and lower in frequency than the first set of resource elements. The UE may receive second control signaling that schedules a data signal to be communicated between the UE and a network node in a set of time-frequency resources. The UE may communicate the data signal according to the second control signaling and the DMRS according to the DMRS pattern.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: January 28, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Raviteja Patchava, Xiaoxia Zhang, Zhifei Fan, Jing Sun, Tao Luo, Junyi Li, Morteza Soltani
  • Patent number: 12212515
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a base station, an indication that demodulation reference signal (DMRS) bundling is to be used for channel estimation by the base station for one or more physical uplink control channel (PUCCH) repetitions, where the indication is a semi-static configuration or a dynamic indication. The UE may transmit, to the base station, the one or more PUCCH repetitions by maintaining a phase continuity among DMRSs of the one or more PUCCH repetitions based at least in part on receiving the indication that DMRS bundling is to be used. Numerous other aspects are described.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: January 28, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Mahmoud Taherzadeh Boroujeni, Tao Luo, Xiaoxia Zhang, Junyi Li, Jing Sun, Wooseok Nam
  • Publication number: 20250031155
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a configuration for a component carrier (CC) configuring the CC for simultaneous transmissions associated with multiple transmission reception points (TRPs). The UE may transmit a power headroom (PHR) report, associated with the CC, that indicates: a first PHR value associated with a first TRP associated with the multiple TRPs (mTRPs) and a second PHR value associated with a second TRP associated with the mTRPs; or a single PHR value associated with at least one of the first TRP or the second TRP. Numerous other aspects are provided.
    Type: Application
    Filed: January 24, 2022
    Publication date: January 23, 2025
    Inventors: Fang YUAN, Wooseok NAM, Yan ZHOU, Mostafa KHOSHNEVISAN, Jelena DAMNJANOVIC, Jing SUN, Tao LUO, Junyi LI
  • Patent number: 11728817
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: August 15, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik S. Gopalakrishnan, Aaron Buchwald
  • Publication number: 20220190836
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Application
    Filed: January 3, 2022
    Publication date: June 16, 2022
    Inventors: Mrunmay TALEGAONKAR, Jorge PERNILLO, Junyi SUN, Praveen PRABHA, Chang-Feng LOI, Yu LIAO, Jamal RIANI, Belal HELAL, Karthik S. GOPALAKRISHNAN, Aaron BUCHWALD
  • Patent number: 11218156
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 4, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik Gopalakrishnan, Aaron Buchwald
  • Publication number: 20210263912
    Abstract: The embodiments of the disclosure disclose a method of data processing based on smart contract and a device. The method includes: determining a current endorsement time based on a generating time point of a previous block in an endorsement blockchain during calling a smart contract; and preprocessing a current transaction processing request based on the current endorsement time to obtain an endorsement processing result, to enable a node other than the endorsement node in the blockchain network to process the current transaction processing request based on the endorsement processing result.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 26, 2021
    Applicant: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Junyi SUN, Yucao WANG, Wei XIAO
  • Publication number: 20200403627
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Mrunmay TALEGAONKAR, Jorge PERNILLO, Junyi SUN, Praveen PRABHA, Chang-Feng LOI, Yu LIAO, Jamal RIANI, Belal HELAL, Karthik Gopalakrishnan, Aaron BUCHWALD
  • Patent number: 10804913
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 13, 2020
    Assignee: INPHI CORPORATION
    Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik Gopalakrishnan, Aaron Buchwald
  • Patent number: D919760
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: May 18, 2021
    Inventors: Ruqi Sun, Junyi Sun