Abstract: This application provides a single-stage voltage-adjustable rectification system with multi-output full-wave rectification, including a rectifier and a control module. The rectifier includes a producing module, an idling switch component, a first transistor component, a second transistor component, a load, and a third transistor component in electrical connection. The producing module is configured for producing alternating input voltage. The first transistor component and the second transistor component are configured for generating, based on the alternating input voltage, DC output voltage. The load is configured for obtaining the DC output voltage.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The embodiments of the disclosure disclose a method of data processing based on smart contract and a device. The method includes: determining a current endorsement time based on a generating time point of a previous block in an endorsement blockchain during calling a smart contract; and preprocessing a current transaction processing request based on the current endorsement time to obtain an endorsement processing result, to enable a node other than the endorsement node in the blockchain network to process the current transaction processing request based on the endorsement processing result.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.