Patents by Inventor Junyi Xu
Junyi Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110479Abstract: The present disclosure provides a multi-factor quantitative analysis method for deformation of a neighborhood tunnel. The method includes the following steps: analyzing monitoring data generated at a tunnel site; simulating collapse occurring at a shallow buried section of a tunnel; determining the degree of influence of each factor on the tunnel and a stratum; and determining quantitative influence of each factor on tunnel deformation. The present disclosure can not only provide an accurate theoretical basis for the construction of the shallow buried section of the small-distance tunnel, but also guarantee safety and cost saving during tunnel construction.Type: ApplicationFiled: February 22, 2023Publication date: April 4, 2024Inventors: Yongjun ZHANG, Fei LIU, Sijia LIU, Junyi WANG, Bin GONG, Yingming WU, Ruiquan LU, Qingsong WANG, Qinghui XU, Xiaoming GUAN, Mingdong YAN, Xiangyang NI, Pingan WANG, Shuguang LI, Lin YANG, Ning NAN, Dengfeng YANG
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Patent number: 11398931Abstract: Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.Type: GrantFiled: January 11, 2021Date of Patent: July 26, 2022Assignee: Marvell Asia Pte LtdInventors: Xing Wu, Yuansheng Jin, Junyi Xu, Jian-Hung Lin, Shaoan Dai
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Publication number: 20210218604Abstract: Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.Type: ApplicationFiled: January 11, 2021Publication date: July 15, 2021Inventors: Xing WU, Yuansheng JIN, Junyi XU, Jian-Hung LIN, Shaoan DAI
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Patent number: 9093134Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.Type: GrantFiled: December 21, 2012Date of Patent: July 28, 2015Assignee: Broadcom CorporationInventors: Binfan Liu, Junyi Xu
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Patent number: 8873647Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.Type: GrantFiled: February 14, 2013Date of Patent: October 28, 2014Assignee: Broadcom CorporationInventors: Binfan Liu, Junyi Xu, Weimin Zhang
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Patent number: 8401092Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.Type: GrantFiled: July 30, 2010Date of Patent: March 19, 2013Assignee: Broadlogic Network Technologies Inc.Inventors: Binfan Liu, Junyi Xu, Weimin Zhang
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Patent number: 8352834Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.Type: GrantFiled: January 5, 2010Date of Patent: January 8, 2013Assignee: BroadLogic Network Technologies Inc.Inventors: Binfan Liu, Junyi Xu
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Publication number: 20110113305Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.Type: ApplicationFiled: January 5, 2010Publication date: May 12, 2011Applicant: BroadLogic Network Technologies Inc.Inventors: Binfan Liu, Junyi Xu
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Patent number: 7809094Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.Type: GrantFiled: October 15, 2007Date of Patent: October 5, 2010Assignee: BroadLogic Network Technologies Inc.Inventors: Junyi Xu, Binfan Liu, Vladimir Radionov, Weimin Zhang
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Publication number: 20090096514Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Applicant: BroadLogic Network Technologies Inc.Inventors: Junyi Xu, Binfan Liu, Vladimir Radionov, Weimin Zhang