Patents by Inventor JUNYUAN LV

JUNYUAN LV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12094875
    Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first field plate, and a second field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate structure is disposed above the second nitride-based semiconductor layer. The first field plate is disposed over the gate structure and is electrically coupled with the source electrode and the drain electrode. The second field plate is disposed over the gate structure and is electrically coupled with the gate structure. The first field plate and the second field plate are parallel with each other. A top surface of the first field plate faces a bottom surface of the second field plate to overlap with each other.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: September 17, 2024
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Xin Zhang, Jianjian Sheng, Junyuan Lv, Zhenzhe Li
  • Publication number: 20230352476
    Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first field plate, and a second field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate structure is disposed above the second nitride-based semiconductor layer. The first field plate is disposed over the gate structure and is electrically coupled with the source electrode and the drain electrode. The second field plate is disposed over the gate structure and is electrically coupled with the gate structure. The first field plate and the second field plate are parallel with each other. A top surface of the first field plate faces a bottom surface of the second field plate to overlap with each other.
    Type: Application
    Filed: October 27, 2021
    Publication date: November 2, 2023
    Inventors: Xin ZHANG, Jianjian SHENG, Junyuan LV, Zhenzhe LI
  • Patent number: 11715946
    Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 1, 2023
    Assignee: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
    Inventors: Yaobin Guan, Jianjian Sheng, Zhenzhe Li, Junyuan Lv
  • Publication number: 20220376494
    Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.
    Type: Application
    Filed: November 30, 2020
    Publication date: November 24, 2022
    Inventors: YAOBIN GUAN, JIANJIAN SHENG, ZHENZHE LI, JUNYUAN LV