Patents by Inventor Junzaburo Shirai

Junzaburo Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5633480
    Abstract: Conductive circuits (copper foil) are provided on both surfaces of a basefilm. A first prepreg is laminated onto both surfaces of the basefilm. A cover lay is provided at an opening portion of the basefilm. The cover lay may extend to a through-hole. The semirigid cover lay, made from polyimide-containing resin material, is placed to cover the opening portion, thermocompressed, and bonded to be laminated onto the surface of the basefilm. A second prepreg having an opening portion whose shape is substantially similar to the opening portion of the first prepreg, is laminated on the first prepreg.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: May 27, 1997
    Assignee: CMK Corporation
    Inventors: Hiromoto Sato, Junzaburo Shirai
  • Patent number: 5629497
    Abstract: A prepreg having an opening portion is placed on a cover lay which covers conductive circuits formed on a basefilm. A copper foil sheet is placed on the prepreg in such a way that the copper foil sheet covers the opening portion. The copper foil sheet has no opening portion. Next, the basefilm, the prepreg, and the copper foil are thermocompressed to become one laminate. After making a hole in the laminate, the laminate is plated, and then a through-hole is formed. A conductive circuit is formed by etching the copper foil sheet.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: May 13, 1997
    Assignee: CMK Corporation
    Inventors: Hiromoto Sato, Junzaburo Shirai
  • Patent number: 5168624
    Abstract: A method of manufacturing a printed wiring board on a cubically molded substrate enables formation of high-precision printed circuits fully compatible with the complex configuration of the cubic substrate. The manufacturing method includes initially forming a conductive layer on the surface of a cubic substrate followed by etching the conductive layer. The method includes the steps of forming electrodeposited resist on the conductive layer, exposing the electrodeposited resist to parallel light beams through a planar photomask, and etching the conductive layer to complete the formation of the printed circuit.
    Type: Grant
    Filed: March 15, 1991
    Date of Patent: December 8, 1992
    Assignee: Nippon CMK Corp.
    Inventor: Junzaburo Shirai