Abstract: A heterojunction FET disclosed herein includes a semi-insulating GaAs substrate, a buffer layer composed of an undoped In.sub.y/2 Al.sub.1-y/2 As layer (0<y<1), and having a film thickness less than or equal to a critical film thickness, a first barrier layer composed of an undoped AlAs layer and an undoped In.sub.y Al.sub.1-y As layer (0<y<1), a channel layer composed of an undoped In.sub.y Ga.sub.1-y As layer (0<y<1), a second barrier layer composed of an N-type In.sub.y Al.sub.1-y As layer (0<y<1), each layer disposed in the order mentioned, on the semi-insulating GaAs substrate, a gate electrode which is selectively disposed on the second barrier layer to form a Schottky junction, and electrodes for a drain and a source, each of which is disposed on the second barrier layer via a contact layer, with said gate electrode therebetween.