Abstract: A multichip package is comprised of a substrate having a grid of input and output pins disposed on an under surface. Power supply and grounding wire layers are embedded in the substrate. An upper surface of the substrate has a plurality of thin wire layers separated by at least one insulating layer. A plurality of via holes in the insulating layer permit conductive interconnection of the wire layers. A plurality of leadless chip carriers on the upper have tape automated bonding leads that are inner lead bonded to the substrate. The chips are directly connected to the substrate and have a plurality of chip carrier terminals on an under surface that connect to the terminal pads. The chip carrier has a cover made of highly heat conductive material that contacts the back side of at least one mounted chip.

Abstract: A multichip package is comprised of a substrate having a grid of input and output pins disposed on an under surface. Power supply and grounding wire layers are embedded in the substrate. An upper surface of the substrate has a plurality of thin wire layers separated by at least one insulating layer. A plurality of via holes in the insulating layer permit conductive interconnection of the wire layers. A plurality of leadless chip carriers on the upper layer have tape automated bonding leads that are inner lead bonded to the substrate. The chips are directly connected to the substrate and have a plurality of chip carrier terminals on an under surface that connect to the terminal pads. The chip carrier has a cover made of highly heat conductive material that contacts the back side of at least one mounted chip.