Abstract: A system and method for facilitating software profiling procedures in a target device includes a target CPU that executes software instructions from target routines of the target device to perform various processing tasks. A program counter of the target device is periodically updated with a current program counter value corresponding to one of the software instructions that is being currently executed by the target CPU. A shadow register is advantageously implemented in the target device to be directly accessible by profiler software on a host computer. The shadow register is periodically updated with a profiling program counter value that corresponds to the current program counter value. The profiler software may then directly and transparently access the shadow register to read the profiling program counter value for performing the software profiling procedures.

Abstract: A system and method for facilitating software profiling procedures in a target device includes a target CPU that executes software instructions from target routines of the target device to perform various processing tasks. A program counter of the target device is periodically updated with a current program counter value corresponding to one of the software instructions that is being currently executed by the target CPU. A shadow register is advantageously implemented in the target device to be directly accessible by profiler software on a host computer. The shadow register is periodically updated with a profiling program counter value that corresponds to the current program counter value. The profiler software may then directly and transparently access the shadow register to read the profiling program counter value for performing the software profiling procedures.

Abstract: A system and method for supporting variable-width memory accesses includes storage registers configured to store transfer data. The storage registers have a pre-determined storage register width. A host interface moves the transfer data to and from the storage registers. The host interface has a data transfer width that is greater than the storage register width. A memory access module analyzes a mode flag that is incorporated into a transfer address. The memory access module performs the memory access operation in a full mode if the mode flag is set to a full access state. Conversely, the memory access module performs the memory access operation in a partial access mode if the mode flag is set to a partial access state. In the partial transfer mode, the transfer data has a data width that is equal to the storage register width. The memory storage module is able to directly access a single one of the storage registers.

Abstract: A system and method for performing an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display processor. The processor subsequently receives an interrupt request for executing a second task that has a higher priority than the first task. A save/restore module responsively stores task states from the host interface into an interface states register. The task states correspond to an interrupted execution point in the first task. The processor temporarily stops the first task to execute the second task. The save/restore module restores the stored task states to the host interface after the second task is completed, and the processor may then efficiently resume the first task.

Abstract: A system and method for performing an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display processor. The processor subsequently receives an interrupt request for executing a second task that has a higher priority than the first task. A save/restore module responsively stores task states from the host interface into an interface states register. The task states correspond to an interrupted execution point in the first task. The processor temporarily stops the first task to execute the second task. The save/restore module restores the stored task states to the host interface after the second task is completed, and the processor may then efficiently resume the first task.

Abstract: A system and method for supporting variable-width memory accesses includes storage registers configured to store transfer data. The storage registers have a pre-determined storage register width. A host interface moves the transfer data to and from the storage registers. The host interface has a data transfer width that is greater than the storage register width. A memory access module analyzes a mode flag that is incorporated into a transfer address. The memory access module performs the memory access operation in a full mode if the mode flag is set to a full access state. Conversely, the memory access module performs the memory access operation in a partial access mode if the mode flag is set to a partial access state. In the partial transfer mode, the transfer data has a data width that is equal to the storage register width. The memory storage module is able to directly access a single one of the storage registers.

Abstract: A system and method for utilizing a remote memory device to perform an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display controller. The processor subsequently receives an interrupt request for executing a second task that has a higher priority than the first task. A save/restore module responsively creates a task handle that represents the interrupted first task states from the display controller. The processor then stores the task handle in a remote memory device that is implemented outside of the display controller to conserve memory resources of the display controller. After the second task has been completed, the processor returns the saved task handle to the save/restore module for restoring the interrupted first task states to the display controller. The display controller may then efficiently resume performing the interrupted first task.

Abstract: A system and method for performing an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display processor. The processor subsequently receives an interrupt request for executing a second task that has a higher priority than the first task. A save/restore module responsively stores task states from the host interface into an interface states register. The task states correspond to an interrupted execution point in the first task. The processor temporarily stops the first task to execute the second task. The save/restore module restores the stored task states to the host interface after the second task is completed, and the processor may then efficiently resume the first task.

Abstract: A method for debugging including the steps of receiving code having a software breakpoint function therein, running the code for the purpose of debugging, monitoring the code to detect the presence of the software breakpoint function, recognizing the software breakpoint function, determining an action to be performed based on the software breakpoint function, and implementing the action. The present invention also includes an apparatus for implementing the method for debugging and a medium embodying a program of instructions for execution by a device to perform the method for debugging.

Abstract: A system and method for performing manual partial transfers of image data includes a display controller with controller logic and a rectangle module. The rectangle module detects write operations to on-screen data in a video memory, and then updates a transfer rectangle to include written data from the foregoing write operations. The controller logic generates a transfer interrupt in response to a transfer trigger event in the display controller for initiating a manual partial transfer operation from the video memory to a display device. A central processing unit from a host electronic device detects the transfer interrupt and responsively coordinates the manual partial transfer operation to transfer rectangle data of the transfer rectangle from the video memory to the display device of the host electronic device.

Abstract: A system and method for performing automatic frame transfers of image data includes a display controller with controller logic and an automatic transfer module. The controller logic detects a transfer trigger event in the display controller for initiating an automatic frame transfer operation of on-screen data from a video memory to a display device. In certain embodiments, the transfer trigger event may be generated by either a write counter or a transfer timer. The automatic transfer module performs automatic transfer configuration procedures to prepare the display device for the automatic frame transfer operation. The automatic transfer module then automatically performs the automatic frame transfer operation to transfer the on-screen data from the video memory to the display device.

Abstract: A system and method for performing manual frame transfers of image data includes an electronic device with a central processing unit, a display device, and a display controller. The display controller includes controller logic that toggles a transfer flag in response to a transfer trigger event in the display controller for initiating a manual frame transfer operation to transfer on-screen data from a video memory of the display controller to the display device. In certain embodiments, the transfer trigger event may be generated by either a write counter or a transfer timer. The central processing unit responsively coordinates the manual frame transfer operation to transfer the on-screen data from the video memory to the display device of the host electronic device.

Abstract: A system and method for detecting memory writes to initiate image data transfers includes a display controller device with a write detector module and controller logic. The write detector module detects write operations from a host central-processing unit to on-screen data in a video memory of the display controller. The write detector module responsively sets a transfer flag to indicate that the on-screen data has been modified. The controller logic then detects that the transfer flag has been set by the write detector module. The controller logic may then efficiently initiate a frame transfer operation for transferring the modified on-screen data from the video memory to a display of a host electronic device.

Abstract: A system and method for detecting memory location modifications to initiate image data transfers includes a display controller device with a location detector module and controller logic. The location detector module detects register write operations from a host central-processing unit to on-screen registers in a controller registers of the display controller. The on-screen registers define where in a video memory of the display controller the on-screen data is stored. The location detector module responsively sets a transfer flag to indicate that one or more memory locations of the on-screen data have been modified. The controller logic then detects that the transfer flag has been set by the location detector module. The controller logic may then efficiently initiate a frame transfer operation for transferring the appropriate on-screen data from the video memory to a display of a host electronic device.

Abstract: A method and apparatus for downscaling digital image data to fit a graphics display device. The method and apparatus provide for sampling a sequence of image data so that (N?M)+/?1 pixels, preferably N?M pixels, of the image data are sampled for every N pixels of said sequence, where M and N are integers and M<N. Preferably, N=2n, where n is a positive integer.

Abstract: A method for debugging including the steps of receiving code having a software breakpoint function therein, running the code for the purpose of debugging, monitoring the code to detect the presence of the software breakpoint function, recognizing the software breakpoint function, determining an action to be performed based on the software breakpoint function, and implementing the action. The present invention also includes an apparatus for implementing the method for debugging and a medium embodying a program of instructions for execution by a device to perform the method for debugging.

Abstract: A computer system includes an operator input device, a central processing unit (CPU), and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller.

Abstract: A computer system includes an operator input device, a central processing unit (CPU), and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller.