Patents by Inventor Juraj Obert
Juraj Obert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240078628Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a high-performance and low-latency implementation of a wavelet-based image compression scheme. A processor may generate, in a single pass for each of a plurality of horizontal and vertical divisions of an image frame, a set of wavelet coefficients for the image frame based on a DWT. The processor may select a set of bits associated with the set of wavelet coefficients to remove based on an entropy coding process. The processor may serialize the set of wavelet coefficients, where the set of serialized wavelet coefficients do not include the set of bits. The processor may output, for a second device, a bitstream including the set of serialized wavelet coefficients.Type: ApplicationFiled: August 14, 2023Publication date: March 7, 2024Inventors: Juraj OBERT, Aravind SRINIVASA RAGHAVAN, Rex PERKINS, Mark Dale HAACK, Janardhan HARYADI RAMESH, Kevin HAWKINS
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Publication number: 20230290035Abstract: A system and method for performing graphics processing is provided. The system and method includes processing an allocation command for a buffer object; reserving processor address space for a data store of the buffer object with uncommitted physical memory in response to the allocation command including a null parameter, and reserving processor address space for a data store of the buffer object with committed physical memory in response to the allocation command including a non-null parameter.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
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Patent number: 11676321Abstract: A method and system for performing graphics processing is provided. The method and system includes storing stencil buffer values in a stencil buffer; generating either or both of a reference value and a source value in a fragment shader; comparing the stencil buffer values against the reference value; and processing a fragment based on the comparing the stencil buffer values against the reference value.Type: GrantFiled: June 29, 2020Date of Patent: June 13, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
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Publication number: 20200327715Abstract: A method and system for performing graphics processing is provided. The method and system includes storing stencil buffer values in a stencil buffer; generating either or both of a reference value and a source value in a fragment shader; comparing the stencil buffer values against the reference value; and processing a fragment based on the comparing the stencil buffer values against the reference value.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
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Patent number: 10699464Abstract: Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.Type: GrantFiled: October 31, 2016Date of Patent: June 30, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
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Patent number: 10417791Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.Type: GrantFiled: June 12, 2018Date of Patent: September 17, 2019Assignee: QUALCOMM IncorporatedInventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
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Patent number: 10186008Abstract: Techniques are described for stereoscopic view generation. A graphics processing unit (GPU) may combine attribute information for two or more corresponding vertices of corresponding primitives in different views. The GPU may process the combined attributed information to generate graphics data for the stereoscopic view.Type: GrantFiled: September 16, 2015Date of Patent: January 22, 2019Assignee: QUALCOMM IncorporatedInventors: Gang Zhong, Vineet Goel, Young In Yeo, Juraj Obert
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Publication number: 20180293761Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.Type: ApplicationFiled: June 12, 2018Publication date: October 11, 2018Inventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
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Patent number: 10019829Abstract: Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.Type: GrantFiled: June 7, 2013Date of Patent: July 10, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Graham Sellers, Pierre Boudier, Juraj Obert
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Patent number: 9984492Abstract: Methods and systems disclosed improve the efficiency of ray tracing. In one aspect, a method of ray tracing in a digital representation of a scene includes segmenting the scene into a plurality of voxels, associating each of the voxels with a node of a bounding volume hierarchy (BVH) representing one or more object primitives within the scene, determining a set of voxels through which the ray passes, determining a set of nodes associated with the set of voxels, determining a deepest common ancestor node of the set of nodes, traversing the hierarchy starting at the deepest common ancestor node to determine a point of intersection between the ray and one of the one or more object primitives; and updating a digital image of the scene based on the determined point of intersection.Type: GrantFiled: August 20, 2015Date of Patent: May 29, 2018Assignee: QUALCOMM IncorporatedInventor: Juraj Obert
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Patent number: 9818221Abstract: At least one processor may organize a plurality of primitives of a scene in a hierarchical data structure, wherein a plurality of bounding volumes are associated with a plurality of nodes of the hierarchical data structure. The at least one processor may rasterize a representation of each of the plurality of bounding volumes to an off-screen render target in the memory. The at least one processor may determine, based at least in part on a pixel in the off-screen render target that maps to a ray in the scene, a non-root node of the hierarchical data structure associated with the pixel as a start node to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine whether the ray in the scene intersects one of the plurality of primitives.Type: GrantFiled: February 25, 2016Date of Patent: November 14, 2017Assignee: QUALCOMM IncorporatedInventor: Juraj Obert
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Patent number: 9805495Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.Type: GrantFiled: February 26, 2016Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Juraj Obert, Tao Wang, Vineet Goel
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Patent number: 9773340Abstract: A method and apparatus for ray tracing may include a method, manufacture and apparatus for ray tracing that may include dividing a render target into a plurality of bins. Next, a visibility pass is performed using ray tracing to generate a visibility stream such that the visibility stream indicates, for each bin of the plurality of bins, which primitives are visible in the bin. Then, for at least one bin of the plurality of bins, each primitive in the bin that is indicated in the visibility stream as being visible in the bin is rendered.Type: GrantFiled: June 12, 2015Date of Patent: September 26, 2017Assignee: QUALCOMM IncorporatedInventors: Murat Balci, Christopher Paul Frascati, Juraj Obert, Hitendra Mohan Gangani, Avinash Seetharamaiah
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Publication number: 20170249779Abstract: At least one processor may organize a plurality of primitives of a scene in a hierarchical data structure, wherein a plurality of bounding volumes are associated with a plurality of nodes of the hierarchical data structure. The at least one processor may rasterize a representation of each of the plurality of bounding volumes to an off-screen render target in the memory. The at least one processor may determine, based at least in part on a pixel in the off-screen render target that maps to a ray in the scene, a non-root node of the hierarchical data structure associated with the pixel as a start node to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine whether the ray in the scene intersects one of the plurality of primitives.Type: ApplicationFiled: February 25, 2016Publication date: August 31, 2017Inventor: Juraj Obert
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Publication number: 20170249771Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.Type: ApplicationFiled: February 26, 2016Publication date: August 31, 2017Inventors: Juraj Obert, Tao Wang, Vineet Goel
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Publication number: 20170243375Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.Type: ApplicationFiled: February 18, 2016Publication date: August 24, 2017Inventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
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Patent number: 9697640Abstract: At least one processor may organize a plurality of primitives in a hierarchical data structure. The at least one processor may rasterize a plurality of bounding volumes associated with non-root nodes of the hierarchical data structure to an off-screen render target. The at least one processor may determine a bounding volume that is intersected by a ray out of the plurality of bounding volumes. The at least one processor may determine a non-root node of the hierarchical data structure that is associated with the bounding volume as a start node in the hierarchical data structure to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine the primitive that is intersected by the ray.Type: GrantFiled: April 21, 2014Date of Patent: July 4, 2017Assignee: QUALCOMM IncorporatedInventors: Juraj Obert, Vineet Goel, Ouns Mouri
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Patent number: 9607425Abstract: A method and apparatus for ray tracing may include using texture pipeline hardware of a GPU to perform ray intersection testing for a first ray and a first shape. Using the texture pipeline hardware to perform ray intersection testing may include calculating a plurality of dot products with the texture pipeline hardware, and determining whether the first ray intersects the first shape based on the plurality of dot products.Type: GrantFiled: October 17, 2014Date of Patent: March 28, 2017Assignee: QUALCOMM IncorporatedInventors: Juraj Obert, Vineet Goel
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Publication number: 20170061670Abstract: Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.Type: ApplicationFiled: October 31, 2016Publication date: March 2, 2017Applicant: Advanced Micro Devices, Inc.Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
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Publication number: 20160364901Abstract: A method and apparatus for ray tracing may include a method, manufacture and apparatus for ray tracing that may include dividing a render target into a plurality of bins. Next, a visibility pass is performed using ray tracing to generate a visibility stream such that the visibility stream indicates, for each bin of the plurality of bins, which primitives are visible in the bin. Then, for at least one bin of the plurality of bins, each primitive in the bin that is indicated in the visibility stream as being visible in the bin is rendered.Type: ApplicationFiled: June 12, 2015Publication date: December 15, 2016Inventors: Murat Balci, Christopher Paul Frascati, Juraj Obert, Hitendra Mohan Gangani, Avinash Seetharamaiah