Patents by Inventor Jurgen Amon

Jurgen Amon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7679120
    Abstract: A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: March 16, 2010
    Assignee: Qimonda, AG
    Inventors: Jurgen Amon, Jurgen Faul, Thomas Ruder, Thomas Schuster
  • Patent number: 7473953
    Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: January 6, 2009
    Assignee: Infineon Technologies AG
    Inventors: Ralf Staub, Jürgen Amon, Norbert Urbansky
  • Publication number: 20080048229
    Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
    Type: Application
    Filed: October 30, 2007
    Publication date: February 28, 2008
    Inventors: Ralf Staub, Jurgen Amon, Norbert Urbansky
  • Patent number: 7326985
    Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: February 5, 2008
    Assignee: Infineon Technologies AG
    Inventors: Ralf Staub, Jürgen Amon, Norbert Urbansky
  • Publication number: 20070205437
    Abstract: A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.
    Type: Application
    Filed: August 31, 2006
    Publication date: September 6, 2007
    Inventors: Jurgen Amon, Jurgen Faul, Thomas Ruder, Thomas Schuster
  • Patent number: 7259060
    Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: August 21, 2007
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Amon, Jürgen Faul, Johann Alsmeier, Matthias Goldbach, Albrecht Kieslich, Ralf Müller, Dirk Offenberg, Thomas Schuster
  • Patent number: 7118955
    Abstract: Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: October 10, 2006
    Assignee: Infineon Technologies AG
    Inventors: Jurgen Amon, Jurgen Faul, Thomas Ruder, Thomas Schuster
  • Patent number: 6967133
    Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 22, 2005
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Amon, Jürgen Faul, Ulrike Gruening, Frank Jakubowski, Thomas Schuster, Rudolf Strasser
  • Publication number: 20050130370
    Abstract: Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.
    Type: Application
    Filed: December 10, 2004
    Publication date: June 16, 2005
    Inventors: Jurgen Amon, Jurgen Faul, Thomas Ruder, Thomas Schuster
  • Publication number: 20050124124
    Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.
    Type: Application
    Filed: November 23, 2004
    Publication date: June 9, 2005
    Inventors: Jurgen Amon, Jurgen Faul, Johann Alsmeier, Matthias Goldbach, Albrecht Kieslich, Ralf Muller, Dirk Offenberg, Thomas Schuster
  • Publication number: 20040192007
    Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
    Type: Application
    Filed: October 23, 2003
    Publication date: September 30, 2004
    Inventors: Ralf Staub, Jurgen Amon, Norbert Urbansky
  • Publication number: 20040115874
    Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).
    Type: Application
    Filed: October 29, 2003
    Publication date: June 17, 2004
    Inventors: Jurgen Amon, Jurgen Faul, Ulrike Gruening, Frank Jakubowski, Thomas Schuster, Rudolf Strasser
  • Patent number: 6368940
    Abstract: A method for fabricating a microelectronic structure includes implanting nitrogen into a semiconductor substrate which is provided with trenches, at least in the region of a main area of the semiconductor substrate. The implantation is intended to be carried out in such a way that a nitrogen concentration at the main area is considerably greater than at the side walls of the trenches. As a result, during subsequent oxidation of the semiconductor substrate, a thinner oxide layer can be formed on the main area, in comparison with the side walls. The oxide layer has a homogeneous transition in the edge region between the main area and the side walls. Implanting nitrogen prior to the oxidation of the semiconductor substrate leads to a uniform oxide layer thickness on the main area.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: April 9, 2002
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Amon, Albrecht Kieslich