Abstract: A method for direct memory access includes: receiving a direct memory access request designating addresses in a data block to be accessed in a memory; randomizing an order of the addresses the data block is accessed; and accessing the memory at addresses in the randomized order. A system for direct memory access is disclosed.

Abstract: An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks, and a power gate control circuit configured to control power gating for each VM block of a plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates a supply voltage from each block of a selected subset of the plurality of VM blocks and allows a retention voltage to power each VM block of a remaining subset of the plurality of VM blocks outside the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block of the remaining subset.

Abstract: An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks, and a power gate control circuit configured to control power gating for each VM block of a plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates a supply voltage from each block of a selected subset of the plurality of VM blocks and allows a retention voltage to power each VM block of a remaining subset of the plurality of VM blocks outside the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block of the remaining subset.

Abstract: A method for direct memory access includes: receiving a direct memory access request designating addresses in a data block to be accessed in a memory; randomizing an order of the addresses the data block is accessed; and accessing the memory at addresses in the randomized order. A system for direct memory access is disclosed.

Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.

Abstract: A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

Abstract: A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

Abstract: Embodiments provide forced-burst voltage regulation for burst mode direct-current-to-direct-current (DC-DC) converters in integrated circuits. The DC-DC converter generates an output voltage and operates in a burst mode to raise the output voltage to a threshold voltage. A controller is coupled to the DC-DC converter. In operation, the DC-DC converter is configured to perform the burst mode based upon a low-voltage detection for the output voltage. The DC-DC converter is further configured to perform the burst mode when a force-burst command is asserted by the controller to the DC-DC converter regardless of a state for the low-voltage detection. For one embodiment, the force-burst command is asserted as a burst control signal from the controller to the DC-DC converter to generate a long quiet period for sensitive actions. For another embodiment, the force-burst command is asserted using enable and refresh control signals to facilitate low-power operation.

Abstract: A memory system is disclosed, comprising a primary memory module, a secondary memory module, and a controller. The controller is configured to identify addresses in the primary memory module requiring correction, and is further configured to receive a memory access request identifying an address in the primary memory module. The controller is configured to determine whether the address is identified as requiring correction and, if it is not, to direct the memory access request to the primary memory module. If the address is identified as requiring correction, the controller is configured to direct the memory access request to the secondary memory module.

Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.

Abstract: According to a first aspect of the present disclosure, a method for facilitating secure communication in a network is conceived, comprising: encrypting, by a source node in the network, a cryptographic key using a device key as an encryption key, wherein said device key is based on a device identifier that identifies a destination node in the network; transmitting, by said source node, the encrypted cryptographic key to the destination node. According to a second aspect of the present disclosure, a corresponding non-transitory, tangible computer program product is provided. According to a third aspect of the present disclosure, a corresponding system for facilitating secure communication in a network is provided.

Abstract: A memory system is disclosed, comprising a primary memory module, a secondary memory module, and a controller. The controller is configured to identify addresses in the primary memory module requiring correction, and is further configured to receive a memory access request identifying an address in the primary memory module. The controller is configured to determine whether the address is identified as requiring correction and, if it is not, to direct the memory access request to the primary memory module. If the address is identified as requiring correction, the controller is configured to direct the memory access request to the secondary memory module.

Abstract: According to a first aspect of the present disclosure, a method is conceived for securing data communicated in a network, the method comprising: receiving, by a destination node in the network, at least one message transmitted by a source node in the network; generating, by said destination node, a session key by executing a one-way function that takes at least a part of a last received message and an initial key as input parameters; using, by said destination node, the session key for encrypting or decrypting said data. Furthermore, according to a second aspect of the present disclosure, a corresponding computer program product is conceived. Furthermore, according to a third aspect of the present disclosure, a corresponding system is conceived.

Abstract: Aspects of the present disclosure are directed to methods, apparatuses and systems involving a switched probe contact. According to an example embodiment, an apparatus includes logic circuitry, a first circuit to communicate signals with the logic circuitry, and a first bond pad connected to the first circuit via a first circuit path. The apparatus also includes a second circuit to communicate signals with the logic circuitry, and a second bond pad connected to the second circuit via a second circuit path. A probe contact is connected to the first bond pad and communicates signals with an external probe, and a switch circuit is connected to the probe contact and the second circuit path. The switch circuit communicates signals between the probe contact and the second circuit path by selectively connecting and disconnecting the probe contact to the second circuit path.

Abstract: According to a first aspect of the present disclosure, a method for facilitating secure communication in a network is conceived, comprising: encrypting, by a source node in the network, a cryptographic key using a device key as an encryption key, wherein said device key is based on a device identifier that identifies a destination node in the network; transmitting, by said source node, the encrypted cryptographic key to the destination node. According to a second aspect of the present disclosure, a corresponding non-transitory, tangible computer program product is provided. According to a third aspect of the present disclosure, a corresponding system for facilitating secure communication in a network is provided.

Abstract: According to a first aspect of the present disclosure, a method for facilitating secure communication in a network is conceived, comprising: encrypting, by a source node in the network, a new cryptographic key using a current cryptographic key as an encryption key; transmitting, by said source node, the encrypted new cryptographic key to a destination node in the network. According to a second aspect of the present disclosure, a method for facilitating secure communication in a network is conceived, comprising: receiving, by a destination node in the network, an encrypted new cryptographic key from a source node in the network; decrypting, by said destination node, the encrypted new cryptographic key using a current cryptographic key as a decryption key. According to a third aspect of the present disclosure, corresponding computer program products are provided. According to a fourth aspect of the present disclosure, a corresponding source node is provided.

Abstract: According to a first aspect of the present disclosure, a method is conceived for securing data communicated in a network, the method comprising: receiving, by a destination node in the network, at least one message transmitted by a source node in the network; generating, by said destination node, a session key by executing a one-way function that takes at least a part of a last received message and an initial key as input parameters; using, by said destination node, the session key for encrypting or decrypting said data. Furthermore, according to a second aspect of the present disclosure, a corresponding computer program product is conceived. Furthermore, according to a third aspect of the present disclosure, a corresponding system is conceived.

Abstract: Aspects of the present disclosure are directed to methods, apparatuses and systems involving a switched probe contact. According to an example embodiment, an apparatus includes logic circuitry, a first circuit to communicate signals with the logic circuitry, and a first bond pad connected to the first circuit via a first circuit path. The apparatus also includes a second circuit to communicate signals with the logic circuitry, and a second bond pad connected to the second circuit via a second circuit path. A probe contact is connected to the first bond pad and communicates signals with an external probe, and a switch circuit is connected to the probe contact and the second circuit path. The switch circuit communicates signals between the probe contact and the second circuit path by selectively connecting and disconnecting the probe contact to the second circuit path.

Abstract: Disclosed is a shift register (200, 400) comprising an input (205), an output (230) and a plurality of register cells (210) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer (220) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels (230, 410) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.

Abstract: Disclosed is a shift register (200, 400) comprising an input (205), an output (230) and a plurality of register cells (210) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer (220) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels (230, 410) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.