Patents by Inventor Jurgen Grafe

Jurgen Grafe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7948071
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 24, 2011
    Assignee: Qimonda AG
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Patent number: 7422930
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: September 9, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Publication number: 20080203575
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Application
    Filed: May 6, 2008
    Publication date: August 28, 2008
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Patent number: 7352057
    Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: April 1, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jurgen Grafe, Sylke Ludewig, Jochen Thomas, Peter Weitz
  • Publication number: 20060091518
    Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.
    Type: Application
    Filed: October 7, 2005
    Publication date: May 4, 2006
    Inventors: Jurgen Grafe, Sylke Ludewig, Jochen Thomas, Peter Weitz
  • Publication number: 20050194674
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Application
    Filed: March 2, 2004
    Publication date: September 8, 2005
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl