Abstract: An optoelectronic arrangement includes a first circuit board, a second circuit board, and an optoelectronic semiconductor chip arranged on the first circuit board, wherein a first electrical contact surface and a second electrical contact surface are formed on a surface of the first circuit board, a first mating contact surface and a second mating contact surface are formed on a surface of the second circuit board, and the first circuit board and the second circuit board connect to one another such that the surface of the first circuit board faces toward the surface of the second circuit board, and the first mating contact surface electrically conductively connects to the first contact surface and the second mating contact surface electrically conductively connects to the second contact surface.

Abstract: A lighting device comprising a plurality of components (2) provided for generating radiation, a plurality of row lines (Z1, Z2) and a plurality of column lines (S1, S2, . . . , S5) is specified, wherein the components are in each case electrically conductively connected to a row line and to a column line and the lighting device is provided for the simultaneous operation of at least two components. A lighting arrangement comprising such a lighting device and a method for operating a lighting device are furthermore specified.

Abstract: A lighting device comprising a plurality of components (2) provided for generating radiation, a plurality of row lines (Z1, Z2) and a plurality of column lines (S1, S2, . . . , S5) is specified, wherein the components are in each case electrically conductively connected to a row line and to a column line and the lighting device is provided for the simultaneous operation of at least two components. A lighting arrangement comprising such a lighting device and a method for operating a lighting device are furthermore specified.

Abstract: A light-emitting diode module includes a carrier and a plurality of optoelectronic semiconductor chips mounted on a carrier top and configured to generate primary radiation. The semiconductor chips are arranged in part at a first distance and in part at a second, greater distance from one another. Between the adjacent semiconductor chips arranged at the first distance from one another there is located a radiation-transmissive first filling for optical coupling. Between the adjacent semiconductor chips arranged at the second distance from one another there is located a radiation-opaque second filling for optical isolation.

Abstract: A lighting device comprising a plurality of components (2) provided for generating radiation, a plurality of row lines (Z1, Z2) and a plurality of column lines (S1, S2, . . . , S5) is specified, wherein the components are in each case electrically conductively connected to a row line and to a column line and the lighting device is provided for the simultaneous operation of at least two components. A lighting arrangement comprising such a lighting device and a method for operating a lighting device are furthermore specified.

Abstract: A carrier (1) for an optoelectronic semiconductor chip comprising: (2) base body (10), which comprises a first main surface (10a) and a second main surface (10b), at least one recess (11), which is introduced into the base body (10) and completely penetrates the base body (10) from the first main surface to the second main surface, and a filler material (12), which is introduced into the at least one recess (11). The base body (10) is formed using silicon of a first conductivity type. The filler material (12) is formed using polycrystalline silicon of a second conductivity type, the polarity of which differs in particular from the first conductivity type. The base body (10) and the filler material (12) are in direct contact with one another at points.

Abstract: An optoelectronic arrangement includes a first circuit board, a second circuit board, and an optoelectronic semiconductor chip arranged on the first circuit board, wherein a first electrical contact surface and a second electrical contact surface are formed on a surface of the first circuit board, a first mating contact surface and a second mating contact surface are formed on a surface of the second circuit board, and the first circuit board and the second circuit board connect to one another such that the surface of the first circuit board faces toward the surface of the second circuit board, and the first mating contact surface electrically conductively connects to the first contact surface and the second mating contact surface electrically conductively connects to the second contact surface.

Abstract: A lighting device comprising a plurality of components (2) provided for generating radiation, a plurality of row lines (Z1, Z2) and a plurality of column lines (S1, S2, . . . , S5) is specified, wherein the components are in each case electrically conductively connected to a row line and to a column line and the lighting device is provided for the simultaneous operation of at least two components. A lighting arrangement comprising such a lighting device and a method for operating a lighting device are furthermore specified.

Abstract: A method serves to produce optoelectronic semiconductor components. A leadframe assemblage includes a number of leadframes. The leadframes each comprise at least two leadframe parts and are connected together at least in part via connecting webs. Electrical connections are attached between neighboring leadframes. A potting body connects the leadframes and the leadframe parts mechanically together. At least some of the connecting webs are removed and/or interrupted, the resulting structure is singulated into the semiconductor components.

Abstract: A light-emitting diode module includes a carrier and a plurality of optoelectronic semiconductor chips mounted on a carrier top and configured to generate primary radiation. The semiconductor chips are arranged in part at a first distance and in part at a second, greater distance from one another. Between the adjacent semiconductor chips arranged at the first distance from one another there is located a radiation-transmissive first filling for optical coupling. Between the adjacent semiconductor chips arranged at the second distance from one another there is located a radiation-opaque second filling for optical isolation.

Abstract: A method serves to produce optoelectronic semiconductor components. A leadframe assemblage includes a number of leadframes. The leadframes each comprise at least two leadframe parts and are connected together at least in part via connecting webs. Electrical connections are attached between neighboring leadframes. A potting body connects the leadframes and the leadframe parts mechanically together. At least some of the connecting webs are removed and/or interrupted, the resulting structure is singulated into the semiconductor components.

Abstract: A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is completely filled by a first interconnect. The trench structure of the capacitor region is only partially filled by a first capacitor electrode and is completely filled by a capacitor dielectric and a second capacitor electrode. In a second dielectric formed thereon, a second interconnect with a contact via is formed, which is connected to the second capacitor electrode.

Abstract: A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

Abstract: Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.

Abstract: An integrated layer stack arrangement, an optical sensor and a method for producing an integrated layer stack arrangement is disclosed. Generally, an integrated layer stack arrangement includes a plurality of layer stacks arranged on top of each other, each layer stack including a metal layer and a dielectric layer arranged; at least one photodiode integrated into the plurality of layer stacks; a trench arranged above the last least one photodiode, the trench extending through at least a portion of the plurality of layer stacks so that light impinging on the plurality of layer stacks impinges on the integrated photodiode along the trench; a first passivation partial layer applied on the plurality of layer stacks; and a second passivation partial layer applied on the plurality of layer stacks and a bottom and walls of the trench.

Abstract: A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source and drain depressions. The electrically conductive filling layer realizes source and drain regions and fills the source and drain depressions at a surface of the depression insulation layer. The gate dielectric is formed at a substrate surface between the source and drain depressions. The gate layer (is formed at a surface of the gate dielectric. The source and drain depressions have, in an upper region, a widening with a predetermined death for realizing defined channel connection regions.

Abstract: A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

Abstract: A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

Abstract: Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.