Abstract: An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

Abstract: The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) includes at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V?), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V?) together with the substrate potential (Vo).

Abstract: An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

Abstract: Method for producing an antifuse in a substrate, a first interconnect being applied to the substrate, a dielectric layer being applied at an end face of the first interconnect, which end face essentially runs vertically with respect to the substrate, a second interconnect being applied in such a way that it adjoins the dielectric layer with an end face, with the result that an antifuse structure is formed.

Abstract: A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are interconnected to form a ring structure. Two measurement pads are in each case provided at the nodes between two resistors. The measurement pads can be used for feeding in current and for measuring voltage according to the known four-point measurement method. The effect of the ring structure is that fewer measurement pads are required, in contrast to the customary series circuit of resistors. By way of example, in the case of a ring structure with four resistors, two measurement pads are advantageously saved. The consequently reduced chip area required for the ring structure is advantageous particularly in the case of test circuits, which can be arranged for example in the narrow sawing frame between two chips.

Abstract: An ESD protection apparatus for limiting a voltage superimposed on an electric useful voltage to an allowable voltage, comprising a plurality of series-connected diodes. The diodes are forward-biased with reference to the useful voltage. Each individual forward-biased diode has a threshold voltage. The sum of the threshold voltages of the series-connected diodes corresponds to the allowable voltage.

Abstract: The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which comprises a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) comprises at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V?), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V?) together with the substrate potential (Vo).

Abstract: The invention relates to a method for producing an antifuse structure in a substrate, a conductive region and a nonconductive region adjoining the latter being formed in the substrate, so that an edge of the conductive region is produced, a dielectric layer being deposited in such a way that it covers at least a part of the edge.

Abstract: Method for producing an antifuse in a substrate, a first interconnect being applied to the substrate, a dielectric layer being applied at an end face of the first interconnect, which end face essentially runs vertically with respect to the substrate, a second interconnect being applied in such a way that it adjoins the dielectric layer with an end face, with the result that an antifuse structure is formed.

Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

Abstract: An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

Abstract: A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

Abstract: A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator layer has a cavity formed therein extending to the main surface of the semiconductor body. A fuse having a fusible part extends from the main surface of the semiconductor body toward an upper surface of the insulator layer at right angles to the main surface of the semiconductor body, and the fuse is embedded in the cavity. A method for producing the semiconductor configuration having the fuse is also described.

Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

Abstract: An integrated dynamic memory includes a memory cell array having memory cells each assigned to one of a plurality of groups. The plurality of groups are divided into defect-free groups having exclusively defect-free memory cells and into defective groups having at least one defective memory cell. The memory further includes a memory configuration table that contains a list of the defect-free groups and an assignment unit that, based upon the entries in the memory configuration table, executes memory accesses only to those memory cells assigned to a defect-free group. The total capacity of the memory module, then, is not fixed once and for all with fabrication, but, rather, results only after a memory test, or may even vary in the course of the module lifetime.

Abstract: A vertical MOS field effect transistor includes a gate disposed in a trench, a channel, and a source and a drain disposed in the substrate on the trench wall. The gate annularly surrounds a drain terminal which extends from the substrate surface as far as the drain disposed on the trench bottom. It is possible to produce vertical transistors with different channel lengths on a substrate with trenches of different widths by employing oblique implantation when producing the gate. A method of producing the vertical field effect transistor is also provided.

Abstract: A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are interconnected to form a ring structure. Two measurement pads are in each case provided at the nodes between two resistors. The measurement pads can be used for feeding in current and for measuring voltage according to the known four-point measurement method. The effect of the ring structure is that fewer measurement pads are required, in contrast to the customary series circuit of resistors. By way of example, in the case of a ring structure with four resistors, two measurement pads are advantageously saved. The consequently reduced chip area required for the ring structure is advantageous particularly in the case of test circuits, which can be arranged for example in the narrow sawing frame between two chips.

Abstract: A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

Abstract: An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

Abstract: Electrical fuses/antifuses in a semiconductor memory configuration, such as in particular a DRAM, are read, instead of with the previously conventional internal voltage, with the voltage that defines the high potential of the bit lines of a memory cell array in the semiconductor memory. The high potential of the bit lines is defined by a voltage that is reduced relative to the internal voltage of the semiconductor memory.