Patents by Inventor Jurgen Michels
Jurgen Michels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11604147Abstract: A layer of amorphous Ge is formed on a substrate using electron-beam evaporation. The evaporation is performed at room temperature. The layer of amorphous Ge has a thickness of at least 50 nm and a purity of at least 90% Ge. The substrate is complementary metal-oxide-semiconductor (CMOS) compatible and is transparent at Long-Wave Infrared (LWIR) wavelengths. The layer of amorphous Ge can be used as a waveguide in chemical sensing and data communication applications. The amorphous Ge waveguide has a transmission loss in the LWIR of 11 dB/cm or less at 8 ?m.Type: GrantFiled: November 9, 2021Date of Patent: March 14, 2023Assignee: Massachusetts Institute of TechnologyInventors: Eveline Postelnicu, Samarth Aggarwal, Kazumi Wada, Jurgen Michel, Lionel C. Kimerling, Michelle L. Clark, Anuradha M. Agarwal
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Patent number: 11581451Abstract: Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).Type: GrantFiled: June 8, 2018Date of Patent: February 14, 2023Assignees: NANYANG TECHNOLOGICAL UNIVERSITY, MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Yiding Lin, Jurgen Michel, Chuan Seng Tan
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Publication number: 20220065793Abstract: A layer of amorphous Ge is formed on a substrate using electron-beam evaporation. The evaporation is performed at room temperature. The layer of amorphous Ge has a thickness of at least 50 nm and a purity of at least 90% Ge. The substrate is complementary metal-oxide-semiconductor (CMOS) compatible and is transparent at Long-Wave Infrared (LWIR) wavelengths. The layer of amorphous Ge can be used as a waveguide in chemical sensing and data communication applications. The amorphous Ge waveguide has a transmission loss in the LWIR of 11 dB/cm or less at 8 ?m.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Applicant: Massachusetts Institute of TechnologyInventors: Eveline Postelnicu, Samarth Aggarwal, Kazumi WADA, Jurgen MICHEL, Lionel C. KIMERLING, Michelle L. Clark, Anuradha M. AGARWAL
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Patent number: 11204327Abstract: A layer of amorphous Ge is formed on a substrate using electron-beam evaporation. The evaporation is performed at room temperature. The layer of amorphous Ge has a thickness of at least 50 nm and a purity of at least 90% Ge. The substrate is complementary metal-oxide-semiconductor (CMOS) compatible and is transparent at Long-Wave Infrared (LWIR) wavelengths. The layer of amorphous Ge can be used as a waveguide in chemical sensing and data communication applications. The amorphous Ge waveguide has a transmission loss in the LWIR of 11 dB/cm or less at 8 ?m.Type: GrantFiled: November 21, 2019Date of Patent: December 21, 2021Assignee: Massachusetts Institute of TechnologyInventors: Eveline Postelnicu, Samarth Aggarwal, Kazumi Wada, Jurgen Michel, Lionel C. Kimerling, Michelle L. Clark, Anuradha M. Agarwal
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Patent number: 11067754Abstract: Optical interconnects can offer higher bandwidth, lower power, lower cost, and higher latency than electrical interconnects alone. The optical interconnect system enables both optical and electrical interconnection, leverages existing fabrication processes to facilitate package-level integration, and delivers high alignment tolerance and low coupling losses. The optical interconnect system provides connections between a photonics integrated chip (PIC) and a chip carrier and between the chip carrier and external circuitry. The system provides a single flip chip interconnection between external circuitry and a chip carrier using a ball grid array (BGA) infrastructure. The system uses graded index (GRIN) lenses and cross-taper waveguide couplers to optically couple components, delivers coupling losses of less than 0.5 dB with an alignment tolerance of ±1 ?m, and accommodates a 2.5× higher bandwidth density.Type: GrantFiled: August 10, 2020Date of Patent: July 20, 2021Assignee: Massachusetts Institute of TechnologyInventors: Lionel C. Kimerling, Jurgen Michel, Anuradha M. Agarwal, Kazumi Wada, Drew Michael Weninger, Samuel Serna
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Publication number: 20210109290Abstract: Optical interconnects can offer higher bandwidth, lower power, lower cost, and higher latency than electrical interconnects alone. The optical interconnect system enables both optical and electrical interconnection, leverages existing fabrication processes to facilitate package-level integration, and delivers high alignment tolerance and low coupling losses. The optical interconnect system provides connections between a photonics integrated chip (PIC) and a chip carrier and between the chip carrier and external circuitry. The system provides a single flip chip interconnection between external circuitry and a chip carrier using a ball grid array (BGA) infrastructure. The system uses graded index (GRIN) lenses and cross-taper waveguide couplers to optically couple components, delivers coupling losses of less than 0.5 dB with an alignment tolerance of ±1 ?m, and accommodates a 2.5× higher bandwidth density.Type: ApplicationFiled: August 10, 2020Publication date: April 15, 2021Inventors: Lionel C. KIMERLING, Jurgen MICHEL, Anuradha M. AGARWAL, Kazumi WADA, Drew Michael Weninger, Samuel Serna
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Patent number: 10962810Abstract: An integrated optical modulator array useful for modulating light at different wavelengths in the same optical band includes multiple GeSi waveguides on a substrate. Each GeSi waveguide has a different width and is coupled to electrodes to form an electro-absorption modulator. A stressor material, such as SiN, disposed between the GeSi waveguides in the optical modulators applies a strain to the GeSi waveguides. Because each GeSi waveguide has a different width, it experiences a different strain. This difference can be a difference in magnitude, type (homogeneous v. inhomogeneous, compressive v. tensile), or both. The different strains shift the bandgaps of the Ge in the GeSi waveguides by different amounts, shifting the optical absorption edges for the GeSi waveguides by different amounts. Put differently, the stressor layer strains each GeSi modulator differently, causing each GeSi modulator to operate at a different wavelength.Type: GrantFiled: September 27, 2019Date of Patent: March 30, 2021Assignee: Massachusetts Institute of TechnologyInventors: Danhao Ma, Yiding Lin, Jurgen Michel
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Patent number: 10680413Abstract: In a method for electrically doping a semiconducting material, a layer of germanium is formed having a germanium layer thickness, while in situ incorporating phosphorus dopant atoms at a concentration of at least about 5×1018 cm?3 through the thickness of the germanium layer during formation of the germanium layer. Additional phosphorus dopant atoms are ex situ incorporated through the thickness of the germanium layer, after formation of the germanium layer, to produce through the germanium layer thickness a total phosphorus dopant concentration of at least about 2×1019 cm?3.Type: GrantFiled: May 1, 2017Date of Patent: June 9, 2020Assignee: Massachusetts Institute of TechnologyInventors: Jonathan T. Bessette, Yan Cai, Rodolfo E. Camacho-Aguilera, Jifeng Liu, Lionel Kimerling, Jurgen Michel
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Publication number: 20200158651Abstract: A layer of amorphous Ge is formed on a substrate using electron-beam evaporation. The evaporation is performed at room temperature. The layer of amorphous Ge has a thickness of at least 50 nm and a purity of at least 90% Ge. The substrate is complementary metal-oxide-semiconductor (CMOS) compatible and is transparent at Long-Wave Infrared (LWIR) wavelengths. The layer of amorphous Ge can be used as a waveguide in chemical sensing and data communication applications. The amorphous Ge waveguide has a transmission loss in the LWIR of 11 dB/cm or less at 8 ?m.Type: ApplicationFiled: November 21, 2019Publication date: May 21, 2020Inventors: Eveline Postelnicu, Samarth Aggarwal, Kazumi WADA, Jurgen MICHEL, Lionel C. KIMERLING, Michelle L. Clark, Anuradha M. AGARWAL
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Publication number: 20200103680Abstract: An integrated optical modulator array useful for modulating light at different wavelengths in the same optical band includes multiple GeSi waveguides on a substrate. Each GeSi waveguide has a different width and is coupled to electrodes to form an electro-absorption modulator. A stressor material, such as SiN, disposed between the GeSi waveguides in the optical modulators applies a strain to the GeSi waveguides. Because each GeSi waveguide has a different width, it experiences a different strain. This difference can be a difference in magnitude, type (homogeneous v. inhomogeneous, compressive v. tensile), or both. The different strains shift the bandgaps of the Ge in the GeSi waveguides by different amounts, shifting the optical absorption edges for the GeSi waveguides by different amounts. Put differently, the stressor layer strains each GeSi modulator differently, causing each GeSi modulator to operate at a different wavelength.Type: ApplicationFiled: September 27, 2019Publication date: April 2, 2020Inventors: Danhao Ma, Yiding Lin, Jurgen Michel
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Publication number: 20200105962Abstract: Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).Type: ApplicationFiled: June 8, 2018Publication date: April 2, 2020Inventors: Yiding LIN, Jurgen MICHEL, Chuan Seng TAN
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Patent number: 10418273Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.Type: GrantFiled: October 11, 2016Date of Patent: September 17, 2019Assignees: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
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Patent number: 10324256Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: GrantFiled: December 11, 2017Date of Patent: June 18, 2019Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Publication number: 20190074214Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.Type: ApplicationFiled: October 11, 2016Publication date: March 7, 2019Applicants: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Yiding Lin, Jurgen Michel
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Publication number: 20180198256Abstract: In a method for electrically doping a semiconducting material, a layer of germanium is formed having a germanium layer thickness, while in situ incorporating phosphorus dopant atoms at a concentration of at least about 5×1018 cm?3 through the thickness of the germanium layer during formation of the germanium layer. Additional phosphorus dopant atoms are ex situ incorporated through the thickness of the germanium layer, after formation of the germanium layer, to produce through the germanium layer thickness a total phosphorus dopant concentration of at least about 2×1019 cm?3.Type: ApplicationFiled: May 1, 2017Publication date: July 12, 2018Applicant: Massachusetts Institute of TechnologyInventors: Jonathan T. Bessette, Yan Cai, Rodolfo E. Camacho-Aguilera, Jifeng Liu, Lionel Kimerling, Jurgen Michel
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Publication number: 20180172903Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: ApplicationFiled: December 11, 2017Publication date: June 21, 2018Applicants: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Patent number: 9915785Abstract: A device includes a substrate, a pedestal extending from the substrate, and a ring resonator disposed on the pedestal above the substrate. The ring resonator has a resonance wavelength greater than 1.5 ?m and includes at least one of silicon and chalcogenide glass. The device can be used as a ring resonator sensor or a light source. The ring resonator is substantially transparent to mid-infrared radiation to reduce optical losses. The pedestal has a narrower width compared to the ring resonator to generate improved interaction between evanescent fields of light in the ring resonator and analytes nearby the ring resonator, thereby increasing sensing sensitivity. In addition, fabrication of the device is compatible with complementary metal-oxide-semiconductor (CMOS) processes and hence is amenable to large scale manufacturing.Type: GrantFiled: May 9, 2017Date of Patent: March 13, 2018Assignee: Massachusetts Institute of TechnologyInventors: Pao Tai Lin, Jurgen Michel, Anuradha Murthy Agarwal
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Patent number: 9874689Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: GrantFiled: January 14, 2015Date of Patent: January 23, 2018Assignees: National University of Singapore, Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Publication number: 20170301817Abstract: A germanium metal-semiconductor-metal (MSM) photodetector is fabricated by growing crystalline germanium from an amorphous silicon seed, supported by an amorphous substrate, at a temperature of about 450° C. In this fabrication, crystalline Ge is grown via selective deposition in geometrically confined channels, where amorphous silicon is disposed as the growth seed. Ge growth extends from the growth seed along the channels to a lithographically defined trench. The Ge emerging out of the channels includes crystalline grains that coalesce to fill the trench, forming a Ge strip that can be used as the active area of a photodetector. One or more Schottky contacts can be formed by a thin tunneling layer (e.g., Al2O3) deposited on the Ge strip and metal contracts formed on the tunneling layer.Type: ApplicationFiled: April 13, 2017Publication date: October 19, 2017Inventors: BRIAN PEARSON, JURGEN MICHEL, LIONEL KIMERLING
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Publication number: 20170242194Abstract: A device includes a substrate, a pedestal extending from the substrate, and a ring resonator disposed on the pedestal above the substrate. The ring resonator has a resonance wavelength greater than 1.5 ?m and includes at least one of silicon and chalcogenide glass. The device can be used as a ring resonator sensor or a light source. The ring resonator is substantially transparent to mid-infrared radiation to reduce optical losses. The pedestal has a narrower width compared to the ring resonator to generate improved interaction between evanescent fields of light in the ring resonator and analytes nearby the ring resonator, thereby increasing sensing sensitivity. In addition, fabrication of the device is compatible with complementary metal-oxide-semiconductor (CMOS) processes and hence is amenable to large scale manufacturing.Type: ApplicationFiled: May 9, 2017Publication date: August 24, 2017Inventors: Pao Tai LIN, Jurgen MICHEL, Anuradha Murthy AGARWAL