Abstract: In a method of displaying graphics subdivided into areas with a foreground and a background, each of which is area-wise switchable to a selectable color, and in which graphics areas are transparently switchable to at least a different display plane, bits specially reserved in the memory for the foreground and background transparent switching can be saved in that a foreground color selected in the area and a background color selected in the area are compared area-wise, and in that those areas of the foreground and/or the background of the graphics are transparently switched in which a predetermined constellation of the selected foreground color and the selected background color is determined.

Abstract: A circuit arrangement is described for converting a parallel data stream into a serial data stream and for intermediate storage and clocked supply of the data stream, which is characterized in that a first shift register (1) is provided in which the parallel data stream is stored in bit frames in dependence upon an externally supplied processor clock and which supplies a serial data stream by means of bit-wise scanning of the stored data, which serial data stream is applied in parallel to all memory locations of a second, bit-wise addressable shift register (2) from which the data stored therein are serially read in dependence upon a serial clock, and which supplies the serial data stream, in that the second shift register (2) is assigned to a load shift register (3) supplying a level indicator which constantly marks the limit between memory cells of the second shift register (2) with valid, stored data and memory cells which are to be newly written with data, and in that storage of the data supplied by the f

Abstract: For a possible flexible adaptation to changing ambient conditions, a circuit arrangement comprising an integrated circuit in which a microprocessor is provided which controls an index generator provided in the integrated circuit for teletext and/or on-screen display functions and which performs control functions of a television apparatus by means of a control interface provided in the integrated circuit is characterized in that a storage interface for a read-only memory outside the integrated circuit is provided in the integrated circuit, and in that the read-only memory comprises at least a part of the program code for the microprocessor and at least a font for the teletext function and possible further index functions.

Abstract: It is often desirable to display characters with a border. This border is generated on-line in accordance with the invention in that for each instantaneous raster line preceding and succeeding raster lines are read and column-wise combined in conformity with the desired border, said combined information being step-wise delayed by a number of raster points. The delayed signals are combined in conformity with the side selected for the border and with the border width, and produce the border signal after suppression at the areas where character information is to be displayed. As a result, aribtrary character shapes can be provided with a selectable border, it only being necessary to store these character shapes without border. Also described is a simple device for carrying out such a method.

Abstract: A circuit arrangement for controlling access to a common memory by two or more processors, one of which is privileged, accelerates and simplifies the execution of the accesses by provision for each processor of its own address register and its own data register. As a result, a processor can process the data read during an access while the next access to the memory is already being carried out for another processor. In the case of write operations, the waiting times are reduced, notably for the non-privileged processors when a write operation is interrupted by a privileged processor, because the data to be written can then be transferred directly to the associated data register.

Abstract: Conventional microprocessors await the data on the bus for acceptance for a given number of processor clock signals after accessing an external device, notably after a read instruction for an external data memory. When a comparatively slow memory is used in conjunction with a fast microprocessor, it may occur that the data is not yet present at the anticipated instant. In microprocessors in which no hold state is provided it is known to reduce the clock frequency during the reading of the external memory until the data is actually available. However, this results in a fluctuating mean clock frequency of the microprocessor so that internal timing members, controlled by the clock, cannot determine defined periods of time. In accordance with the invention, the clock frequency is reduced during the part of the operating cycle of the microprocessor during which an external device can be accessed, the microprocessor operating at the maximum clock frequency during the remainder of the cycle.