Abstract: In a circuit arrangement composed of highly integrated chips for a microprogrammed data processing device of the type including an arithmetic and control unit, at least one read-only memory, at least one random access memory, connecting contacts on the chips for connection to peripheral units, and a bus connecting the chips together, each contact is connected to a function selecting unit whose operating state is controlled by a microprogram contained in the read-only memory to selectively connect the contact in the arrangement as either an input contact or an output contact. The function selecting unit includes for each contact a bistable circuit and a gating circuit controlled by the microprogram to determine when each contact constitutes an input or an output terminal.

Abstract: A circuit arrangement for selectively adding or subtracting two binary coded decimal numbers exclusively by means of addition operations, in which addition involves adding a binary coded decimal value corresponding to the decimal value "6" to each digit of one of the numbers to be added and adding a binary coded decimal value corresponding to the decimal value "10" when the addition of corresponding digits of the two numbers and the value "6" does not produce a carry, and in which subtraction involves forming the unit complement to each digit of the subtrahend, adding together the unit complement of each digit, to the corresponding digit of the minuend, and a value of "1", and then adding the binary coded decimal value corresponding to the decimal value "10" when the previous addition does not produce a carry.

Abstract: In a circuit arrangement for an integrated data processing system, which arrangement is composed of various function blocks formed on integrated circuit chips containing MOS components, the function blocks are distributed among the chips and all of the chips are provided with identical connection zones for permitting connection of a collecting bus. Preferably, all chips are fabricated to have substantially the same degree of circuit complexity.

Abstract: In a circuit arrangement composed of chips containing highly integrated MOS circuit components for a data processing device, the arrangement including a first chip containing a central arithmetic and control unit, a plurality of further chips each containing a memory, and a bus connecting the chips, each further chip is provided with its own address register for addressing the memory on that chip, and the register is capable of being set to contain any desired address word and to selectively count through a sequence of successive address words under control of counting pulses, each address word identifying a respective word location of the associated memory.

Abstract: In a circuit arrangement composed of a plurality of highly integrated MOS circuit chips, for use in a data processing device, one chip being an arithmetic and control unit and further chips containing memories, each further chip is also provided with an address register capable of storing a selected memory location address and an address selecting the memory of a selected memory chip for read-out and arranged to count through the successive memory location addresses and to change the memory selecting address after the count reaches the last memory location address, such counting being effected by counting pulses.