Abstract: An integrated write/read memory consisting of a matrix of normal memory cells organized in rows and columns. The memory further includes a smaller matrix of redundant memory cells having their own column and row address decoders that can be engaged to replace any faulty memory cells in the normal matrix. The redundant address decoders are connected to all the address lines by means of fusible links so that any redundant address gate can be programmed to emulate the address of a faulty memory cell. The system further includes logic controls that automatically disables any normal memory address if a redundant memory cell is programmed to take its place.

Abstract: An integrated dynamic write-read memory includes at least one redundant row and/or column initially excluded from normal operation of the memory but available for normal operation as a replacement. At least one row decoder is connected to the memory matrix and at least one column decoder is connected to the memory matrix for addressing. A column address pulse is fed to the memory matrix for initiating addressing by matrix columns and a row address pulse is fed to the memory matrix for initiating addressing by matrix rows. A normal data path leading out of the memory matrix includes a tristate output connected to the normal data path and actuated by addressing with the stored digital data. Another decoder is connected in the normal data path between the memory matrix and the tristate output with an output connected to the tristate output.

Abstract: Integrated semiconductor circuit with a dynamic read-write memory having a memory matrix composed of identical memory cells addressable via row and column decoders with respect to the individual memory cells, the addressing of the individual matrix rows being initiated by a row address strobe while the addressing of the individual matrix columns is initiated by a column address strobe, the addressing being such that during read-out, simultaneously, the information contents of at least two of the memory cells intended for data storage is processed and temporarily stored in an interim register, and including, in addition, a shift register exclusively operated by the column address strobe for the serial transmission of the information contents simultaneously obtained from the memory matrix to the data output of the memory, including means for controlling the data output of the memory via the column address strobe so that the information present at the data output of the memory and made available by the shift reg