Patents by Inventor Jurgen Weidenhofer

Jurgen Weidenhofer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and probe card configuration for testing a plurality of integrated circuits in parallel
    Patent number: 6853206
    Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Michael Hübner, Gunnar Krause, Justus Kuhn, Jochen Müller, Peter P{hacek over (o)}chmüller, Jürgen Weidenhöfer
  • Test configuration and test method for testing a plurality of integrated circuits in parallel
    Patent number: 6762611
    Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: July 13, 2004
    Assignee: Infineon Techologies AG
    Inventors: Michael Hübner, Gunnar Krause, Justus Kuhn, Jochen Müller, Peter Pöchmüller, Jürgen Weidenhöfer
  • Method and probe card configuration for testing a plurality of integrated circuits in parallel
    Publication number: 20040124863
    Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
    Type: Application
    Filed: December 15, 2003
    Publication date: July 1, 2004
    Applicant: Infineon Technologies AG
    Inventors: Michael Hubner, Gunnar Krause, Justus Kuhn, Jochen Muller, Peter Pochmuller, Jurgen Weidenhofer
  • Test configuration and test method for testing a plurality of integrated circuits in parallel
    Publication number: 20020089341
    Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
    Type: Application
    Filed: December 5, 2001
    Publication date: July 11, 2002
    Inventors: Michael Hubner, Gunnar Krause, Justus Kuhn, Jochen Muller, Peter Pochmuller, Jurgen Weidenhofer