Abstract: Disclosed herein is a data processing system comprising a processing unit operable to process data to generate a sequence of outputs, wherein the processing unit is configurable, when generating a sequence of outputs, such that the data processing for generating an output in the sequence of outputs will be performed within a respective processing period for the output. A controller for the processing unit is configured to cause the processing unit, when generating a sequence of outputs, during a respective processing period for at least one output in the sequence of outputs, to also undergo one or more fault detection test(s) such that both processing of data for the output and fault detection testing is performed during the respective processing period for the output.

Abstract: A data processing system (1) comprises a plurality of processing units (11) and a controller (30) operable to allocate processing units of the plurality of processing units into respective groups of the processing units, wherein each group of processing units comprises a set of one or more of the processing units of the plurality of processing units. The data processing system further comprises an arbiter (31, 32) for each group of processing units for controlling access by virtual machines (33, 34) that require processing operations to the processing units of the group of processing units that the arbiter has been allocated.

Abstract: A data processing system (1) comprises a plurality of, e.g. graphics, processing units (11), and a management circuit (12) associated with the processing units and operable to configure the processing units of the plurality of processing units into respective groups of the processing units. The management circuit (12) is configured to always operate with a high level of fault protection, but the groups of the processing units can be selectively operated with either a higher level of fault protection or a lower level of fault protection, by selectively subjecting them to fault detection testing (60).

Abstract: A data processing system that comprises plural processing units is disclosed. The system includes functional units, the functional units having different processing capacities. A set of one or more processing units can operate in combination with one of the functional units according to a processing capacity required for the set of one or more processing units.

Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.

Abstract: A data processing system comprising a plurality of processing units. Each processing unit comprises a set of plural functional units and an internal communications network that routes communications between the functional units in a particular sequence order of the functional units. Each processing unit is connected to at least one other processing unit via a communications bridge that has at least two connections, a first connection that routes communications between a first pair of network nodes of the pair of processing units, and a separate, second connection that routes communications between a second, different pair of network nodes of the pair of processing units. Each connected pair of network nodes comprises network nodes having different positions in the internal communications network sequence order of the network nodes and/or network nodes associated with functional units of different types.

Abstract: A data processing system comprising a plurality of processing units that are configurable as different partitions of processing units. The system comprises a multicast communication network for routing cache communications within a partition of processing unit. A cache controller of one of the processing units within a partition is configurable as a master cache controller for a set of caches within the partition. The master cache controller is operable to issue requests over the multicast communication network to all of the caches in the set of caches at the same time. The multicast communication network is configured to combine response signals from the different processing units within the partition to provide a combined response signal to the master cache controller that represents an overall request-response status for the caches to which the request was issued.

Abstract: In a data processing system in which varying numbers of channels for accessing a memory can be configured, the communications channel to use for an access to the memory is determined by mapping a memory address associated with the memory access to an intermediate address within an intermediate address space, selecting, based on the number of channels configured for use to access the memory, a mapping operation to use to determine from the intermediate address which channel to use for the memory access, and using the selected mapping operation to determine from the intermediate address which channel to use for the memory access.

Abstract: A data processing system comprising a plurality of processing units. Each processing unit comprises a set of plural functional units and an internal communications network that routes communications between the functional units in a particular sequence order of the functional units. Each processing unit is connected to at least one other processing unit via a communications bridge that has at least two connections, a first connection that routes communications between a first pair of network nodes of the pair of processing units, and a separate, second connection that routes communications between a second, different pair of network nodes of the pair of processing units. Each connected pair of network nodes comprises network nodes having different positions in the internal communications network sequence order of the network nodes and/or network nodes associated with functional units of different types.

Abstract: A data processing system comprising a plurality of processing units that are configurable as different partitions of processing units. The system comprises a multicast communication network for routing cache communications within a partition of processing unit. A cache controller of one of the processing units within a partition is configurable as a master cache controller for a set of caches within the partition. The master cache controller is operable to issue requests over the multicast communication network to all of the caches in the set of caches at the same time. The multicast communication network is configured to combine response signals from the different processing units within the partition to provide a combined response signal to the master cache controller that represents an overall request-response status for the caches to which the request was issued.

Abstract: Disclosed herein is a data processing system comprising a processing unit operable to process data to generate a sequence of outputs, wherein the processing unit is configurable, when generating a sequence of outputs, such that the data processing for generating an output in the sequence of outputs will be performed within a respective processing period for the output. A controller for the processing unit is configured to cause the processing unit, when generating a sequence of outputs, during a respective processing period for at least one output in the sequence of outputs, to also undergo one or more fault detection test(s) such that both processing of data for the output and fault detection testing is performed during the respective processing period for the output.

Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.

Abstract: A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.

Abstract: A graphics processing system comprises a pair of graphics processing units that are connected to each other via communications bridges that can allow communication between the connected graphics processing units. One of the graphics processing units is operable to act as a master graphics processing unit controlling graphics processing operations on the other graphics processing unit which is operable as a slave graphics processing unit to perform graphics processing operations under the control of the master graphics processing unit. Each graphics processing unit of the pair of graphics processing units is also capable of operating in a standalone mode, in which the graphics processing unit operates independently of the other graphics processing unit to perform a graphics processing task.

Abstract: Apparatus comprises data compression circuitry to process a set of data values, the data compression circuitry comprising: detector circuitry to detect, for each of n complementary groups of m data values of the set of data values, a first subset of the groups for which the data values in the group have a predetermined pattern of data values, where m and n are integers and m×n is the number of data values in the set of data values; generator circuitry to generate a compressed data packet comprising at least: a representation of a second subset of the groups, the second subset being each of then complementary groups other than groups in the first subset; and an indication of a group position, with respect to the set of data values, of each group in the second subset of groups. Complementary decompression apparatus is also described.

Abstract: Apparatus comprises data compression circuitry to process a set of data values, the data compression circuitry comprising: detector circuitry to detect, for each of n complementary groups of m data values of the set of data values, a first subset of the groups for which the data values in the group have a predetermined pattern of data values, where m and n are integers and m×n is the number of data values in the set of data values; generator circuitry to generate a compressed data packet comprising at least: a representation of a second subset of the groups, the second subset being each of then complementary groups other than groups in the first subset; and an indication of a group position, with respect to the set of data values, of each group in the second subset of groups. Complementary decompression apparatus is also described.

Abstract: A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.