Abstract: A computing system includes a low-profile chassis a motherboard disposed therein and at least one full-size circuit board coupled to the motherboard within the chassis. A method and another computing system are disclosed.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: Method and apparatus are provided for controlling electrical current supplied to an electronic device, such as a computer system. The method includes drawing up to a predetermined amount of an electrical input current from a first current source, and supplying a first portion of the drawn electrical input current to the electronic device, wherein the amount of the first portion may change over time to supply the amount of electrical current demanded by the electronic device without exceeding the predetermined amount. A second portion is supplied to charge an energy storage device during a period that the first portion is less than the predetermined amount. The stored energy device is discharged, as needed, to supply supplemental electrical current to the electronic device. A power supply including an energy storage device, such as a rechargeable battery, may be used to carry out the method.

Abstract: Embodiments of the invention provide a novel and non-obvious method, system and computer program product for securing of leased resources on a computer. In one embodiment of the invention, a computer for securing resources may comprise at least one processor, a plurality of resources, wherein each resource is associated with configuration data and a programmable logic device connected to each of the plurality of resources. The programmable logic device may be configured for determining whether a resource is leased, reading un-encoded configuration data from a resource, and sending the configuration data to a first unit, if the resource is not leased. The programmable logic device may further be configured for reading encoded configuration data from a resource, decoding the configuration data, sending the configuration data that was decoded to a first unit, and logging use of the resource by the first unit, if the resource is leased.

Abstract: A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (Vref—test) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.

Abstract: This invention enables authenticated communications (transactions) to take place on a standard I2C bus without requiring modification of existing I2C devices. Read and write transactions occurring on the bus are authenticated using an Authentication Agent and a shared secret key. In addition to allowing verification of the legitimacy of the transactions, the authentication of the I2C transactions enhances the reliability and serviceability of the bus and devices on the bus by allowing the Baseboard Management Controller (BMC) to quickly determine and pinpoint errors.

Abstract: A computing system includes a semiconductor which sources/sinks current to/from components within the system, an in-circuit semiconductor on-resistance characterization circuit which measures the on-resistance of the semiconductor, and a processor which periodically or continuously engages the characterization circuit over the life of the semiconductor to obtain a series of on-resistance measurements. Depending on the type of semiconductor used, or depending on arbitrary design limitations, the computing system predicts semiconductor failure based on either a relative mode or an absolute mode. The relative mode is useful when using FET's since on-resistance values vary significantly. In the relative mode, an optional NVRAM is used to store one or more on-resistance measurements which may serve as a reference for assuring proper circuit operation within tolerable deviations from the reference.

Abstract: Methods and apparatus that may be utilized to improve the scalability of multi-processor systems are provided. Data packets constructed in accordance with a defined coherence protocol may be encapsulated in standard I/O packets. As a result, the same interconnect fabric may be used to route coherent data traffic and I/O data traffic.