Patents by Inventor Justin D. Shepherdson
Justin D. Shepherdson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074177Abstract: Microelectronic devices include a region with a tiered stack that includes insulative, conductive, and non-conductive structures arranged in tiers. The insulative structures vertically alternate with both the conductive and the non-conductive structures. Each of the conductive structures is vertically spaced from another of the conductive structures by at least one of the non-conductive structures and at least two of the insulative structures. A composition of the non-conductive structures differs from a composition of the insulative structures. In methods of fabrication, a precursor stack is formed to include the insulative structures vertically alternating with first and second non-conductive structures. In a region of the precursor stack, the first non-conductive structures are removed, forming voids between multi-structure tier groups. Conductive structures are formed in the voids. Electronic systems are also disclosed.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Inventors: David H. Wells, Justin D. Shepherdson, Swapnil A. Lengade, Collin Howder, Dheeraj Kumar, Andrew L. Li
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Publication number: 20230413563Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Publication number: 20230389318Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Collin Howder, Justin D. Shepherdson, Chet E. Carter
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Publication number: 20230387229Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Inventors: Everett A. McTeer, Farrell M. Good, John M. Meldrim, Jordan D. Greenlee, Justin D. Shepherdson, Naiming Liu, Yifen Liu
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Patent number: 11751396Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: GrantFiled: January 20, 2022Date of Patent: September 5, 2023Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Patent number: 11737275Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.Type: GrantFiled: April 16, 2021Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventors: Collin Howder, Justin D. Shepherdson, Chet E. Carter
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Patent number: 11705385Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.Type: GrantFiled: July 6, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Indra V. Chary, Chet E. Carter, Anilkumar Chandolu, Justin B. Dorhout, Jun Fang, Matthew J. King, Brett D. Lowe, Matthew Park, Justin D. Shepherdson
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Publication number: 20230062403Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent.Type: ApplicationFiled: October 22, 2021Publication date: March 2, 2023Applicant: Micron Technology, Inc.Inventors: Alyssa N. Scarbrough, John D. Hopkins, Chet E. Carter, Justin D. Shepherdson, Collin Howder, Joshua Wolanyk
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Publication number: 20230039517Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material.Type: ApplicationFiled: August 6, 2021Publication date: February 9, 2023Applicant: Micron Technology, Inc.Inventors: Alyssa N. Scarbrough, John D. Hopkins, Purnima Narayanan, Vinayak Shamanna, Justin D. Shepherdson
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Publication number: 20230005956Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.Type: ApplicationFiled: September 9, 2022Publication date: January 5, 2023Applicant: Micron Technology, Inc.Inventors: John D. Hopkins, Justin D. Shepherdson, Collin Howder, Jordan D. Greenlee
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Patent number: 11538822Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.Type: GrantFiled: June 18, 2019Date of Patent: December 27, 2022Assignee: Micron Technology, Inc.Inventors: John D. Hopkins, Justin D. Shepherdson, Collin Howder, Jordan D. Greenlee
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Publication number: 20220336485Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: Collin Howder, Justin D. Shepherdson, Chet E. Carter
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Publication number: 20220139958Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: January 20, 2022Publication date: May 5, 2022Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Patent number: 11264404Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: GrantFiled: June 17, 2020Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Publication number: 20210399006Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: June 17, 2020Publication date: December 23, 2021Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Publication number: 20210343624Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.Type: ApplicationFiled: July 6, 2021Publication date: November 4, 2021Applicant: Micron Technology, Inc.Inventors: Indra V. Chary, Chet E. Carter, Anilkumar Chandolu, Justin B. Dorhout, Jun Fang, Matthew J. King, Brett D. Lowe, Matthew Park, Justin D. Shepherdson
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Patent number: 11069598Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.Type: GrantFiled: June 18, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Indra V. Chary, Chet E. Carter, Anilkumar Chandolu, Justin B. Dorhout, Jun Fang, Matthew J. King, Brett D. Lowe, Matthew Park, Justin D. Shepherdson
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Publication number: 20200402890Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.Type: ApplicationFiled: June 18, 2019Publication date: December 24, 2020Applicant: Micron Technology, Inc.Inventors: Indra V. Chary, Chet E. Carter, Anilkumar Chandolu, Justin B. Dorhout, Jun Fang, Matthew J. King, Brett D. Lowe, Matthew Park, Justin D. Shepherdson
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Publication number: 20200402993Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.Type: ApplicationFiled: June 18, 2019Publication date: December 24, 2020Applicant: Micron Technology, Inc.Inventors: John D. Hopkins, Justin D. Shepherdson, Collin Howder, Jordan D. Greenlee