Abstract: Conformal approaches for fabricating contacts, and semiconductor structures having conformal metal contacts, are described. In an example, an integrated circuit structure includes a nanowire or fin coupled to or including a source or drain structure. A dielectric layer is above the source or drain structure. An opening is in the dielectric layer and extends into the source or drain structure, the opening having a bottom and sidewalls. A conductive liner is along the bottom and the sidewalls of the opening. The conductive liner has a thickness variation of less than 10% throughout the conductive liner with respect to the bottom and the sidewalls of the opening, respectively. A conductive fill is on the conductive liner and in a remainder of the opening. A ratio of an area of the conductive fill to the conductive liner in a cross-sectional perspective is at most 3:1.

Abstract: An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.

Abstract: Integrated circuit structures having dual stress gates are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires, and a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires. An NMOS gate electrode is over the first vertical stack of horizontal nanowires, the NMOS gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires. A PMOS gate electrode is over the second vertical stack of horizontal nanowires, the PMOS gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires. The tensile layer of the NMOS gate electrode is not included in the PMOS gate electrode.

Abstract: Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. The conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.

Abstract: An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.