Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.

Abstract: A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.

Abstract: Methods, systems, and devices for in-memory associative processing are described. An apparatus may receive a set of instructions that indicate a first vector and a second vector as operands for a computational operation. The apparatus may select, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing. The apparatus may write the first vector and the second vector to a set of planes each comprising an array of content-addressable memory cells based on the selected vector mapping scheme.

Abstract: Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.

Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

Abstract: Methods, systems, and devices for in-memory associative processing are described. An apparatus may receive a set of instructions that indicate a first vector and a second vector as operands for a computational operation. The apparatus may select, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing. The apparatus may write the first vector and the second vector to a set of planes each comprising an array of content-addressable memory cells based on the selected vector mapping scheme.

Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.

Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.

Abstract: A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.

Abstract: A technique of receiving a write transaction directed to a group of memory parcels of a memory device from a client source. The technique determines a state of a first indicator used to indicate which one of two data structures contains a newer mapping of the group of memory parcels, while the other data structure contains an older mapping of the group of memory parcels. The technique determines a state of a second indicator used to indicate which one of the two data structures is in current use for the group of memory parcels and compares the states of the two indicators. When a data structure in current use does not contain the newer mapping, the technique changes the state of the second indicator to the state of the first indicator. The technique writes content of the write transaction to storage locations based on the newer mapping.

Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.

Abstract: A group of sectors of a memory is provisioned for a logical volume such that an unprovisioned capacity of the memory interleaves at least a subset of the group of sectors to provide proximity disturb isolation. A request to access the memory is received, the request including a logical address within the logical volume. A sector within the group of sectors is identified, the sector corresponding to the logical address, and the requested access is performed in the sector within the group of sectors.

Abstract: Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location.

Abstract: Methods, systems, and devices for indication-based avoidance of defective memory cells are described. A non-volatile memory component may store information regarding one or more memory cells of a volatile memory component that a host device for the volatile memory component is to avoid accessing. The one or more memory cells may be defective for example. The device may transmit, to the non-volatile memory component, a request for an indication of the one or more memory cells of the volatile memory component that the host device is to avoid accessing, and the non-volatile memory may transmit such an indication to the host device. The host device may refrain from writing or reading from the one or more memory cells of the volatile memory component.