Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure may include forming a trench in a dielectric region; forming a TFR element in the trench, the TFR element including a laterally-extending TFR region and a TFR ridge extending upwardly from a laterally-extending TFR region; depositing at least one metal layer over the TFR element; and patterning the at least one metal layer and etching the at least one metal layer using a metal etch to define a pair of metal TFR heads over the TFR element, wherein the metal etch also removes at least a portion of the upwardly-extending TFR ridge. The method may also include forming at least one conductive TFR contact extending through the TFR element and in contact with a respective TFR head to thereby increase a conductive path between the respective TFR head and the TFR element.

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure may include forming a trench in a dielectric region; forming a TFR element in the trench, the TFR element including a laterally-extending TFR region and a TFR ridge extending upwardly from a laterally-extending TFR region; depositing at least one metal layer over the TFR element; and patterning the at least one metal layer and etching the at least one metal layer using a metal etch to define a pair of metal TFR heads over the TFR element, wherein the metal etch also removes at least a portion of the upwardly-extending TFR ridge. The method may also include forming at least one conductive TFR contact extending through the TFR element and in contact with a respective TFR head to thereby increase a conductive path between the respective TFR head and the TFR element.

Abstract: A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

Abstract: A method of forming interconnects in a semiconductor device is provided. A mask including first and second openings is formed over a non-conductive structure. An etch is performed through the mask openings to define (a) a via trench having a via trench width and (b) an interconnect trench having a smaller width than the via trench width. A fill layer is deposited over the structure and (a) fills only a partial width of the via trench to thereby define via trench cavity and (b) fills the full width of the interconnect trench. A further etch is performed through the via trench cavity to form a via opening extending downwardly from the via trench. The remaining fill layer material is removed. The interconnect trench, via trench, and via opening are metallized to form a trench interconnect, a via interconnect, and a via extending downwardly from the via interconnect.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer.

Abstract: The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved.

Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

Abstract: In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module may include: depositing a dielectric barrier layer across at least two structures; depositing a second dielectric layer atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material into the trench and bridging across the resulting at least two exposed copper surfaces.

Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

Abstract: A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.

Abstract: The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.

Abstract: A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.