Patents by Inventor Justin Huttula

Justin Huttula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230337406
    Abstract: An electronic device comprises a heat source and a heat distribution structure coupled to the heat source to distribute heat generated by the heat source during operation of the electronic device.
    Type: Application
    Filed: December 23, 2020
    Publication date: October 19, 2023
    Inventors: Ritu BAWA, Ruander CARDENAS, Kathiravan D, Jia Yan GO, Chin Kung GOH, Jeff KU, Prakash Kurma RAJU, Baomin LIU, Twan Sing LOO, Mikko MAKINEN, Columbia MISHRA, Juha PAAVOLA, Prasanna PICHUMANI, Daniel RAGLAND, Kannan RAJA, Khai Ern SEE, Javed SHAIKH, Gokul SUBRAMANIAM, George Baoci SUN, Xiyong TIAN, Hua YANG, Mark CARBONE, Vivek PARANJAPE, Nehakausar PINJARI, Hari Shanker THAKUR, Christopher MOORE, Gustavo FRICKE, Justin HUTTULA, Gavin SUNG, Sammi WY LIU, Arnab SEN, Chun-Ting LIU, Jason Y. JIANG, Gerry JUAN, Shih Wei NIEN, Lance LIN, Evan KUKLINSKI
  • Patent number: 11774489
    Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Publication number: 20210302489
    Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Publication number: 20210235603
    Abstract: A circuit board and vapor chamber are disclosed. Connectors couple the vapor chamber to a circuit board. The connectors extend from the bottom of the vapor chamber. The connectors fix the vapor chamber to the circuit board such that the bottom of the vapor chamber thermally couples to a heat source on the circuit board. The circuit board has a connector assembly that couples to the vapor chamber.
    Type: Application
    Filed: February 26, 2021
    Publication date: July 29, 2021
    Inventors: Justin HUTTULA, Bala SUBRAMANYA, Juha PAAVOLA, Mark CARBONE, Todd SMITH, Kari MANSUKOSKI, Samarth ALVA, Satyajit Siddharay KAMAT, Nagaraj K
  • Patent number: 11061068
    Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Publication number: 20210136956
    Abstract: Disclosed embodiments are relate to heat transfer devices or heat exchangers for computing systems, and in particular, to heat pipes for improved thermal performance at a cold plate interface. A thermal exchange assembly includes a heat pipe (HP) directly coupled to a cold plate. The HP includes a window, which is a recessed or depressed portion of the HP. The window is attached to the cold plate at a window section of the cold plate. The cold plate is configured to be placed on a semiconductor device that generates heat during operation. The cold plate transfers the heat to the HP with less thermal resistance than existing HP solutions. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 18, 2020
    Publication date: May 6, 2021
    Inventors: Juha Paavola, Columbia Mishra, Justin Huttula, Mark Carbone
  • Publication number: 20210112673
    Abstract: Examples relate to computing devices or apparatuses and to corresponding methods for a computing device. A computing device comprises a display unit comprising a display of the computing device. The computing device further comprises a kickstand. The kickstand is mechanically coupled to the display unit via a sliding mechanism, such that the display unit is adjustable relative to the kickstand along the sliding mechanism.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Justin HUTTULA, Aleksander MAGI, Juha PAAVOLA, Karl HAMBERGER, James RAUPP
  • Patent number: 10866264
    Abstract: An interconnect structure is provided which includes: a member having a first end coupled to a test card, and a second end opposite the first end; and a contact tip at the second end of the member, the contact tip to removably attach to another interconnect structure of a device under test, where a modulus of elasticity of the member varies along a length of the member.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Publication number: 20190212363
    Abstract: An interconnect structure is provided which includes: a member having a first end coupled to a test card, and a second end opposite the first end; and a contact tip at the second end of the member, the contact tip to removably attach to another interconnect structure of a device under test, where a modulus of elasticity of the member varies along a length of the member.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 11, 2019
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Publication number: 20190170810
    Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Inventors: Pooya Tadayon, Justin Huttula
  • Patent number: 7362310
    Abstract: According to some embodiments, a keyboard may be moved to a location behind a display.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Brian A. Wilk, Shawn S. McEuen, Justin Huttula, Alton W. Hezeltine
  • Publication number: 20060055675
    Abstract: According to some embodiments, a keyboard may be moved to a location behind a display.
    Type: Application
    Filed: September 13, 2004
    Publication date: March 16, 2006
    Inventors: Brian Wilk, Shawn McEuen, Justin Huttula, Alton Hezeltine