Abstract: A programmable write equalization circuit includes a first digital clock that is used as a reference to indicate data rate, a second digital clock used to indicate write equalization quantization, a look-up table used to store waveforms used in equalizing the input from the first digital clock domain to the second digital clock domain, a counter used to indicate the number of bits within the look-up table that are to be used for each translation, a polarity detector used to detect the current state of the input data, a non-return-to-zero (NRZ) filter used to indicate the placement of data transitions and non-transitions, and a software interface including programmable registers to control each one of the parameters within the equalization circuit.

Abstract: A programmable write equalization circuit includes a first digital clock that is used as a reference to indicate data rate, a second digital clock used to indicate write equalization quantization, a look-up table used to store waveforms used in equalizing the input from the first digital clock domain to the second digital clock domain, a counter used to indicate the number of bits within the look-up table that are to be used for each translation, a polarity detector used to detect the current state of the input data, a non-return-to-zero (NRZ) filter used to indicate the placement of data transitions and non-transitions, and a software interface including programmable registers to control each one of the parameters within the equalization circuit.

Abstract: A non-volatile storage subsystem comprises a media I/O controller, a media access channel, and movable storage media. A non-volatile disk storage subsystem bas a read channel coupling a disk controller to a disk head assembly. A read channel interfacing subsystem is provided as part of the storage subsystem, and the read channel interfacing subsystem interfaces a disk controller to the read channel. The read channel interfacing subsystem comprises a set of process units and a pipeline manager.

Abstract: A method of data transfer in a data processing system having at least one source buffer and at least one destination buffer. The source buffer includes a plurality of data blocks, each data block having an address and being for storage of data including an identifier uniquely identifying that data block. The destination buffer includes a plurality of data blocks corresponding to the data blocks of the source buffer, each destination block having an address and being for storage of data. Each source block identifier is a function of a corresponding destination block address.