Abstract: An integrated circuit input buffer is provided, which includes a differential buffer, first and second average value circuits and a feedback amplifier. The input buffer is selectively operable in a differential operating mode and a single-ended operating mode. The differential amplifier has first and second buffer inputs and first and second buffer outputs. The first and second average value circuits have inputs coupled to the first and second buffer outputs, respectively. The feedback amplifier has first and second differential inputs coupled to outputs of the first and second average value circuits, respectively, and has an amplifier output. The amplifier output is coupled to the second buffer input when the input buffer is in the single-ended operating mode and is decoupled from the second buffer input when the input buffer is in the differential operating mode.

Abstract: A circuit configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to change a DC level of at least one of the inputs of the differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.