Abstract: The synthesis of various pyrazino[1?,2?:1,5]pyrrolo[2,3-b]-indole-1,4-dione analogs has been successfully implemented in the present application. From these efforts, compounds having the structure of Formula I-c: or a pharmaceutically acceptable salt, tautomer, or stereoisomer thereof, wherein R1, R2, R4-R8, R3?, R6?, and n are as defined herein, are provided. These biologically active derivatives have been further used to prepare cell-specific drug conjugates effective in treating various diseases including cancer.

Abstract: A digital Low Drop-Out regulator includes: an event-driven circuit for generating a trigger signal by asynchronously detecting whether an output voltage is out of a threshold range to generate a first error information signal and a first control signal; a time-driven circuit for generating a second error information signal by detecting a change in the output voltage synchronized with a clock signal, and generating a second control signal by combining the first and second error information signals; a clock/trigger control circuit for generating the clock signal having a first or second cycle based on the trigger signal and the first and second error information signals; a first array driver for controlling driving force of the output voltage in response to the first control signal; and a second array driver for controlling the driving force of the output voltage in response to the second control signal.

Abstract: A digital LDO regulator includes: a pulse control circuit for generating a proportional control signal based on an error code, generating an integral control signal that toggles during a first section, which includes an initialization section and an integration section, based on the proportional control signal, and generating a state information signal that defines a steady state section, the initialization section, and the integration section; a proportional control circuit for outputting a first drive signal by multiplying the error code by a proportional gain factor based on the proportional control signal; an integral control circuit for outputting a second drive signal by multiplying the error code by an integral gain factor based on the state information signal and the integral control signal; and a driver for adjusting the output voltage in response to the first drive signal and the second drive signal.

Abstract: Methods for chemoselective modification of a target molecule comprising an amine N-oxide in a biological sample are provided. Aspects of the methods include selectively reacting the amine N-oxide group of the target molecule with a boron agent, where the reacting reduces the amine N-oxide to an amine to produce a modified target molecule. Modification of the target molecule using the subject methods may produce an activated target molecule, e.g., a detectable or bioactive. In some cases, chemoselective modification leads to cleavage of the modified target molecule to produce a first target fragment and a second target fragment. Also provided are compositions useful in practicing various embodiments of the subject methods.

Abstract: The present application provides, among other things, compounds, compositions and methods for treating various diseases including cancer.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: The present application provides, among other things, a compound of Formula I-a and/or I-b, or a pharmaceutically acceptable salt thereof, wherein the variables are defined in the specification. The compounds of the invention are useful for treating various diseases including cancer.

Abstract: A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.

Abstract: A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.

Abstract: A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.

Abstract: The present application provides, among other things, compounds, compositions and methods for treating various diseases including cancer.