Patents by Inventor Justin M. Schauer
Justin M. Schauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8818271Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.Type: GrantFiled: December 9, 2013Date of Patent: August 26, 2014Assignee: Oracle International CorporationInventors: Justin M. Schauer, Robert David Hopkins, II, Robert J. Drost
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Publication number: 20140099892Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicant: Oracle International CorporationInventors: Justin M. Schauer, Robert David Hopkins, II, Robert J. Drost
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Patent number: 8644759Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.Type: GrantFiled: January 6, 2009Date of Patent: February 4, 2014Assignee: Oracle America, Inc.Inventors: Justin M. Schauer, Robert David Hopkins, Robert J. Drost
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Patent number: 7979754Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.Type: GrantFiled: January 12, 2009Date of Patent: July 12, 2011Assignee: Oracle America, Inc.Inventors: Robert J. Drost, Ronald Ho, Justin M. Schauer
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Patent number: 7871833Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.Type: GrantFiled: November 9, 2009Date of Patent: January 18, 2011Assignee: Oracle America, Inc.Inventors: Alex Chow, Robert D. Hopkins, Justin M. Schauer
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Publication number: 20100171554Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.Type: ApplicationFiled: January 6, 2009Publication date: July 8, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: Justin M. Schauer, Robert David Hopkins, Robert J. Drost
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Patent number: 7750709Abstract: One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.Type: GrantFiled: January 5, 2007Date of Patent: July 6, 2010Assignee: Oracle America, Inc.Inventors: Justin M. Schauer, Robert D. Hopkins
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Publication number: 20100060299Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.Type: ApplicationFiled: November 9, 2009Publication date: March 11, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: Alex Chow, Robert D. Hopkins, Justin M. Schauer
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Patent number: 7649255Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.Type: GrantFiled: December 6, 2006Date of Patent: January 19, 2010Assignee: Sun Microsystems, Inc.Inventors: Alex Chow, Robert D. Hopkins, Justin M. Schauer
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Patent number: 7636361Abstract: One embodiment of the present invention provides a system that asynchronously controls sending data items from a sender to a receiver. This system includes a set of sending FIFOs, a set of receiving FIFOs, as well as a shared data path between the sender and the receiver. The system also includes a set of control paths that operate in parallel between the sender and the receiver, wherein a given control path controls the transmission of data items between a corresponding sending FIFO and a corresponding receiving FIFO through the shared data path. The system further includes a round-robin scheduling mechanism which activates one control path at a time in a predetermined sequence. An activated control path asynchronously controls the sending of a data item from a corresponding sending FIFO to a corresponding receiving FIFO.Type: GrantFiled: September 27, 2005Date of Patent: December 22, 2009Assignee: Sun Microsystems, Inc.Inventors: Jo C. Ebergen, Justin M. Schauer, Robert D. Hopkins, Ivan E. Sutherland
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Publication number: 20090193295Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.Type: ApplicationFiled: January 12, 2009Publication date: July 30, 2009Applicant: SUN MICROSYSTEMS, INC.Inventors: Robert J. Drost, Ronald Ho, Justin M. Schauer
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Patent number: 7425836Abstract: In a method for determining capacitance, a first time-varying signal is driven on a first terminal of a first capacitor and a second time-varying signal is driven on a first terminal of a second capacitor, where the first time-varying signal and the second time-varying signal have a pre-determined phase relationship with each other. These signals are received on second terminals of the first capacitor and the second capacitor and demodulated using a periodic signal to produce demodulated signals. This periodic signal has the same fundamental frequency as the first time-varying signal and the second time-varying signal. A DC component in the demodulated signals is then determined by filtering the demodulated signals, and the sign of the DC component is used to determine a relative capacitance of the first capacitor and the second capacitor.Type: GrantFiled: August 23, 2006Date of Patent: September 16, 2008Assignee: Sun Microsystems, Inc.Inventors: Alex Chow, Robert D. Hopkins, Justin M. Schauer
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Publication number: 20080061801Abstract: In a method for determining capacitance, a first time-varying signal is driven on a first terminal of a first capacitor and a second time-varying signal is driven on a first terminal of a second capacitor, where the first time-varying signal and the second time-varying signal have a pre-determined phase relationship with each other. These signals are received on second terminals of the first capacitor and the second capacitor and demodulated using a periodic signal to produce demodulated signals. This periodic signal has the same fundamental frequency as the first time-varying signal and the second time-varying signal. A DC component in the demodulated signals is then determined by filtering the demodulated signals, and the sign of the DC component is used to determine a relative capacitance of the first capacitor and the second capacitor.Type: ApplicationFiled: August 23, 2006Publication date: March 13, 2008Inventors: Alex Chow, Robert D. Hopkins, Justin M. Schauer