Abstract: Disclosed herein is system for buffering processor interrupts from active input devices, such as Bluetooth devices, so that they are aligned with a video refresh rate. The system may include a processor that operates in a first operating mode (e.g., a low power mode) and, in response to an interrupt request, switch to a second operating mode (e.g., a higher power mode). The first operating mode may be different from the second operating mode (e.g., each with a different level of power consumption). The system may also include a video subsystem, in communication with the processor, that provides video information at a refresh rate. The system may also include an input subsystem, such as a wireless communication system, in communication with the processor, that receives an activity trigger representing an activity of a input device, such as a human input device, and provides, based on the refresh rate, the activity trigger to the processor as the interrupt request.

Abstract: Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.

Abstract: Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.