Abstract: A nanopore sensing device comprises a planar structure provided with plural fluidic passages extending between the first and second chambers. The planar structure supports nanopores in membranes across respective passages and sensor electrodes are arranged to sense a fluidic electrical potential in respective passages between the nanopores and the second chamber. The passages comprise planar fluidic resistor portions between the sensor electrode and the second chamber, the planar fluidic resistor portions extending in a planar direction of the planar structure and being configured to form a fluidic resistor.

Abstract: Light weight fiber-reinforced polymeric structural building panels and methods; sized, configured for fabrication of non-portable wall structures permanently fixed to natural base. The panel main body, and studs, can be fabricated separately, then assembled to each other to complete panel fabrication. Methods for making the main body are hand lay-up, or pultrusion. Studs are typically pultruded, and subsequently prepared having consistent thickness, flat surface, across the width of the stud end wall which is to be mounted to the main body. Foam blocks are between inner and outer layers of the panel. Foam blocks can be prepared in block clusters before assembly to the main body. In the main body, a fibrous layer is between each pair of next adjacent foam blocks. Intercostals extend “y” and “z” dimensions transverse to the length of the main body. Studs can be mounted to the main body using adhesive, mechanical fasteners, or both.

Abstract: Devices for improved nanopore sensing are described. An example device has a structure arranged to separate an analyte reservoir and an outlet chamber. An example device has a structure arranged to separate an analyte reservoir and an outlet chamber. The structure can include an array of nanopore structures, each nanopore structure comprising a passage for fluid connection through the structure between the analyte reservoir and outlet chamber. Control terminals can be arranged for applying a control signal to alter the electrical potential difference across that nanopore structure. Some embodiments include an electronic circuit configured to detect a signal from an electrical transduction element at each nanopore structure. Additional structural features and methods of operating and making the devices are described.

Abstract: There is disclosed a nanopore support structure comprising a wall layer comprising walls defining a plurality of wells, and overhangs extending from the walls across each of the wells, the overhang defining an aperture configured to support a membrane suitable for insertion of a nanopore. There is further disclosed a nanopore sensing device comprising a nanopore support structure, and methods of manufacturing the nanopore support structure and the nanopore sensing device.

Abstract: Light weight fiber-reinforced polymeric structural building panels and methods; sized, configured for fabrication of non-portable wall structures permanently fixed to natural base. The panel main body, and studs, can be fabricated separately, then assembled to each other to complete panel fabrication. Methods for making the main body are hand lay-up, or pultrusion. Studs are typically pultruded, and subsequently prepared having consistent thickness, flat surface, across the width of the stud end wall which is to be mounted to the main body. Foam blocks are between inner and outer layers of the panel. Foam blocks can be prepared in block clusters before assembly to the main body. In the main body, a fibrous layer is between each pair of next adjacent foam blocks. Intercostals extend “y” and “z” dimensions transverse to the length of the main body. Studs can be mounted to the main body using adhesive, mechanical fasteners, or both.

Abstract: Devices for improved nanopore sensing are described. An example device has a structure arranged to separate an analyte reservoir and an outlet chamber. An example device has a structure arranged to separate an analyte reservoir and an outlet chamber. The structure can include an array of nanopore structures, each nanopore structure comprising a passage for fluid connection through the structure between the analyte reservoir and outlet chamber. Control terminals can be arranged for applying a control signal to alter the electrical potential difference across that nanopore structure. Some embodiments include an electronic circuit configured to detect a signal from an electrical transduction element at each nanopore structure. Additional structural features and methods of operating and making the devices are described.

Abstract: Methods and apparatus for forming apertures in a solid state membrane using dielectric breakdown are provided. In one disclosed arrangement a plurality of apertures are formed. The membrane comprises a first surface area portion on one side of the membrane and a second surface area portion on the other side of the membrane. Each of a plurality of target regions comprises a recess or a fluidic passage opening out into the first or second surface area portion. The method comprises contacting all of the first surface area portion of the membrane with a first bath comprising ionic solution and all of the second surface area portion with a second bath comprising ionic solution. A voltage is applied across the membrane via first and second electrodes in respective contact with the first and second baths comprising ionic solutions to form an aperture at each of a plurality of the target regions in the membrane.

Abstract: Methods and apparatus for forming apertures in a solid state membrane using dielectric breakdown are provided. In one disclosed arrangement a plurality of apertures are formed. The membrane comprises a first surface area portion on one side of the membrane and a second surface area portion on the other side of the membrane. Each of a plurality of target regions comprises a recess or a fluidic passage opening out into the first or second surface area portion. The method comprises contacting all of the first surface area portion of the membrane with a first bath comprising ionic solution and all of the second surface area portion with a second bath comprising ionic solution. A voltage is applied across the membrane via first and second electrodes in respective contact with the first and second baths comprising ionic solutions to form an aperture at each of a plurality of the target regions in the membrane.

Abstract: Methods and apparatus for forming apertures in a solid state membrane using dielectric breakdown are provided. In one disclosed arrangement a plurality of apertures are formed. The membrane comprises a first surface area portion on one side of the membrane and a second surface area portion on the other side of the membrane. Each of a plurality of target regions comprises a recess or a fluidic passage opening out into the first or second surface area portion. The method comprises contacting all of the first surface area portion of the membrane with a first bath comprising ionic solution and all of the second surface area portion with a second bath comprising ionic solution. A voltage is applied across the membrane via first and second electrodes in respective contact with the first and second baths comprising ionic solutions to form an aperture at each of a plurality of the target regions in the membrane.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.