Patents by Inventor Justin Prayogo

Justin Prayogo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Common bus data flow for serially chained devices
    Patent number: 11736313
    Abstract: In described examples, a circuit includes a system bus controller having a first downstream port and is configured to generate a first downstream frame responsive to a first local bus transmission received by a first local bus controller, and to generate a second downstream frame responsive to a second local bus transmission received by a second local bus controller. The system bus controller is configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame and is configured to initiate transmission of the downstream aggregate frame at the first downstream port. The system bus controller is adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame and is configured to generate a first upstream transmission responsive to the first upstream frame and to generate the second upstream transmission responsive to the second upstream frame.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: August 22, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vijaya Ceekala, Xin Liu, Justin Prayogo, Sinjeet Parekh
  • Common Bus Data Flow for Serially Chained Devices
    Publication number: 20220029851
    Abstract: In described examples, a circuit includes a system bus controller having a first downstream port and is configured to generate a first downstream frame responsive to a first local bus transmission received by a first local bus controller, and to generate a second downstream frame responsive to a second local bus transmission received by a second local bus controller. The system bus controller is configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame and is configured to initiate transmission of the downstream aggregate frame at the first downstream port. The system bus controller is adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame and is configured to generate a first upstream transmission responsive to the first upstream frame and to generate the second upstream transmission responsive to the second upstream frame.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Vijaya Ceekala, Xin Liu, Justin Prayogo, Sinjeet Parekh
  • Common bus data flow for serially chained devices
    Patent number: 11171804
    Abstract: In described examples, a circuit includes a system bus controller having a first downstream port and is configured to generate a first downstream frame responsive to a first local bus transmission received by a first local bus controller, and to generate a second downstream frame responsive to a second local bus transmission received by a second local bus controller. The system bus controller is configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame and is configured to initiate transmission of the downstream aggregate frame at the first downstream port. The system bus controller is adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame and is configured to generate a first upstream transmission responsive to the first upstream frame and to generate the second upstream transmission responsive to the second upstream frame.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vijaya Ceekala, Xin Liu, Justin Prayogo, Sinjeet Parekh
  • Common Bus Data Flow for Serially Chained Devices
    Publication number: 20200374152
    Abstract: In described examples, a circuit includes a system bus controller having a first downstream port and is configured to generate a first downstream frame responsive to a first local bus transmission received by a first local bus controller, and to generate a second downstream frame responsive to a second local bus transmission received by a second local bus controller. The system bus controller is configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame and is configured to initiate transmission of the downstream aggregate frame at the first downstream port. The system bus controller is adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame and is configured to generate a first upstream transmission responsive to the first upstream frame and to generate the second upstream transmission responsive to the second upstream frame.
    Type: Application
    Filed: October 23, 2019
    Publication date: November 26, 2020
    Inventors: Vijaya Ceekala, Xin Liu, Justin Prayogo, Sinjeet Parekh