Abstract: An integrated circuit and method for setting non-overlap time in a staggered dual output driver relies upon selection from a plurality of delay paths. A cross-conduction prevention circuit provides a first output signal to a first feedback path and a second output signal to a second feedback path. A plurality of delay paths are selectively inserted into one or both of the feedback paths. Non-overlap times for the driver are detected for each of the tested delay paths. In one or both feedback paths, a tested delay path is set for indefinite or permanent use by the staggered dual output driver.

Abstract: A non-overlap circuit is provided for a controller of a switching power supply. The controller includes a clock input coupled to a clocking signal, an enable input, a first drive output, and a second drive output. A current source senses the drive outputs, and in response, provides a current source output that switches on and off. A timing capacitor, coupled to the current source, charges when the current source is on. A switch discharges the timing capacitor when the current source is off. A voltage comparator compares the charge level on the timing capacitor to a reference voltage, and outputs a trigger signal to the enable input of the controller when the charge level on the timing capacitor exceeds the reference voltage. When one drive output switches logic state in response to the clocking signal, the current source charges the timing capacitor until the trigger signal causes the other drive output to switch logic state.