Patents by Inventor Justin R. WEBER
Justin R. WEBER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352598Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).Type: ApplicationFiled: June 30, 2023Publication date: November 2, 2023Applicant: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Patent number: 11784239Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.Type: GrantFiled: December 14, 2016Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Sean T. Ma, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Willy Rachmady, Gilbert W. Dewey, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Patent number: 11764306Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.Type: GrantFiled: September 13, 2021Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Patent number: 11658072Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.Type: GrantFiled: July 26, 2021Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
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Publication number: 20230102219Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.Type: ApplicationFiled: September 17, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Arnab Sen Gupta, Matthew V. Metz, Hui Jae Yoo, Justin R. Weber, Van H. Le, Jason C. Retasket, Abhishek A. Sharma, Noriyuki Sato, Yu-Jin Chen, Eric Mattson, Edward O. Johnson, JR.
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Publication number: 20220336284Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.Type: ApplicationFiled: June 23, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: Aaron Lilak, Sean Ma, Justin R. Weber, Rishabh Mehandru, Stephen M. Cea, Patrick Morrow, Patrick H. Keys
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Patent number: 11404319Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.Type: GrantFiled: August 24, 2017Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Sean Ma, Justin R. Weber, Rishabh Mehandru, Stephen M. Cea, Patrick Morrow, Patrick H. Keys
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Publication number: 20210408299Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Applicant: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Publication number: 20210351078Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Applicant: Intel CorporationInventors: Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
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Patent number: 11152514Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.Type: GrantFiled: September 29, 2017Date of Patent: October 19, 2021Assignee: INTEL CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Patent number: 11075119Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.Type: GrantFiled: March 30, 2017Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
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Patent number: 10892335Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.Type: GrantFiled: December 1, 2016Date of Patent: January 12, 2021Assignee: Intel CorporationInventors: Sean T. Ma, Willy Rachmady, Gilbert W. Dewey, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Publication number: 20200357929Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.Type: ApplicationFiled: September 29, 2017Publication date: November 12, 2020Applicant: INTEL CORPORATIONInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Publication number: 20200279910Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.Type: ApplicationFiled: December 15, 2017Publication date: September 3, 2020Applicant: INTEL CORPORATIONInventors: Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel, Seung Hoon Sung, Glenn A. Glass, Jack T. Kavalieros, Tahir Ghani
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Publication number: 20200235013Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.Type: ApplicationFiled: August 24, 2017Publication date: July 23, 2020Applicant: Intel CorporationInventors: Aaron Lilak, Sean Ma, Justin R. Weber, Rishabh Mehandru, Stephen M. Cea, Patrick Morrow, Patrick H. Keys
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Publication number: 20200185501Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.Type: ApplicationFiled: December 1, 2016Publication date: June 11, 2020Applicant: Intel CorporationInventors: Sean T. Ma, Willy Rachmady, Gilbert W. Dewey, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Publication number: 20200044059Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.Type: ApplicationFiled: December 14, 2016Publication date: February 6, 2020Applicant: Intel CorporationInventors: Sean T. Ma, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Willy Rachmady, Gilbert W. Dewey, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Patent number: 10535770Abstract: Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.Type: GrantFiled: September 24, 2014Date of Patent: January 14, 2020Assignee: Intel CorporationInventors: Uygar E. Avci, Rafael Rios, Kelin J. Kuhn, Ian A. Young, Justin R. Weber
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Publication number: 20190326175Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.Type: ApplicationFiled: March 30, 2017Publication date: October 24, 2019Applicant: Intel CorporationInventors: Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
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Publication number: 20170358658Abstract: Embodiments of the invention include metal oxide metal field effect transistors (MOMFETs) and methods of making such devices. In embodiments, the MOMFET device includes a source and a drain with a channel disposed between the source and the drain. According to an embodiment, the channel has at least one confined dimension that produces a quantum confinement effect in the channel. In an embodiment, the MOMFET device also includes a gate electrode that is separated from the channel by a gate dielectric. According to embodiments, the band-gap energy of the channel may be modulated by changing the size of the channel, the material used for the channel, and/or the surface termination applied to the channel. Embodiments also include forming an type device and a P-type device by controlling the work-function of the source and drain relative to the conduction band and valance band energies of the channel.Type: ApplicationFiled: September 26, 2014Publication date: December 14, 2017Inventors: Rafael RIOS, Kelin J. KUHN, Seiyon KIM, Justin R. Weber