Patents by Inventor Justin S. Legakis

Justin S. Legakis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9922457
    Abstract: A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 20, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Justin S. Legakis, Emmett M. Kilgariff, Michael C. Shebanow
  • Patent number: 9123173
    Abstract: In a raster stage of a graphics pipeline, a method for rasterizing non-rectangular tile groups. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level by generating a non-rectangular footprint comprising a set of pixels related to the graphics primitive. The graphics primitive is then rasterized at a second level by accessing the set of pixels and determining covered pixels out of the set of pixels. The raster stage subsequently outputs the covered pixels for rendering operations in a subsequent stage of the graphics processor.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: September 1, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Justin S. Legakis, Franklin C. Crow, John S. Montrym, Douglas A. Voorhies
  • Publication number: 20140160126
    Abstract: A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 12, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Justin S. LEGAKIS, Emmett M. KILGARIFF, Michael C. SHEBANOW
  • Patent number: 8698811
    Abstract: A method for traversing pixels of an area is described. The method includes the steps of traversing a plurality of pixels of an image using a first boustrophedonic pattern along a predominant axis, and, during the traversal using the first boustrophedonic pattern, traversing a plurality of pixels of the image using a second boustrophedonic pattern. The second boustrophedonic pattern is nested within the first boustrophedonic pattern.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: Franklin C. Crow, Justin S. Legakis, Jeffrey R. Sewall
  • Patent number: 8599202
    Abstract: A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: December 3, 2013
    Assignee: Nvidia Corporation
    Inventors: Justin S. Legakis, Emmett M. Kilgariff, Michael C. Shebanow
  • Patent number: 8169437
    Abstract: A system and method for dividing three-dimensional patches into tasks for processing receives control points defining a three dimensional patch and determines if a number of vertices of the three dimensional patch is greater than a maximum value. When the number of vertices is not greater than the maximum value, the three dimensional patch is output as a single task. When the number of vertices is greater than the maximum value, the three dimensional patch is divided into multiple tasks that each include a number of vertices that is not greater than the maximum value and the multiple tasks are output.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: May 1, 2012
    Assignee: NVIDIA Corporation
    Inventors: Justin S. Legakis, Subodh Kumar
  • Patent number: 8120607
    Abstract: A system and method for stitching a boundary transition region of a patch produces a graphics primitive topology for the boundary transition region of the patch. A first number of vertices is computed for an inside edge of the boundary transition region using a first tessellation level of detail (LOD) of the inside edge. A second number of vertices is computed for an outside edge of the boundary transition region using a second tessellation LOD of the outside edge. A portion of the first number of vertices and the second number of vertices are merged based on a stitching pattern to produce a set of vertices for the boundary transition region. The set of vertices is stitched to produce an ordered list representing the graphics primitive topology.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: February 21, 2012
    Assignee: NVIDIA Corporation
    Inventors: Justin S. Legakis, Henry Packard Moreton
  • Patent number: 8059128
    Abstract: A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: November 15, 2011
    Assignee: Nvidia Corporation
    Inventors: Justin S. Legakis, Mark J. French, Steven E. Molnar, Lukito Muliadi
  • Publication number: 20100079454
    Abstract: A system and method for performing tessellation in a single pass through a graphics processor divides the processing resources within the graphics processor into sets for performing different tessellation operations. Vertex data and tessellation parameters are routed directly from one processing resource to another instead of being stored in memory. Therefore, a surface patch description is provided to the graphics processor and tessellation is completed in a single uninterrupted pass through the graphics processor without storing intermediate data in memory.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Inventors: Justin S. Legakis, Emmett M. Kilgariff, Henry Packard Moreton
  • Patent number: 7542042
    Abstract: A new method of operating a fragment shader to produce complex video content comprised of a video image or images, such as from a DVD player, that overlays a fragment shader-processed background. Pixels are fragment shader-processed during one loop or set of loops through a texture processing stations to produce a fragment shader-processed background. Then, at least some of those pixels are merged with the video or images to produce complex video content. The resulting complex image is then made available for further processing.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: June 2, 2009
    Assignee: NVIDIA Corporation
    Inventors: Roger L. Allen, Rui M. Bastos, Karim M. Abdalla, Justin S. Legakis
  • Patent number: 7522169
    Abstract: A graphics processing unit has a set of parallel processing units. A primitive pipeline delivers tiles of a primitive to selected processing units of the set of processing units. An attribute pipeline distributes attributes to the selected processing units when the end of the primitive is reached, while withholding attributes from the remaining processing units of the set of processing units.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: April 21, 2009
    Assignee: Nvidia Corporation
    Inventors: Lukito Muliadi, Justin S. Legakis
  • Publication number: 20070296726
    Abstract: In a raster stage of a graphics pipeline, a method for rasterizing non-rectangular tile groups. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level by generating a non-rectangular footprint comprising a set of pixels related to the graphics primitive. The graphics primitive is then rasterized at a second level by accessing the set of pixels and determining covered pixels out of the set of pixels. The raster stage subsequently outputs the covered pixels for rendering operations in a subsequent stage of the graphics processor.
    Type: Application
    Filed: June 23, 2006
    Publication date: December 27, 2007
    Inventors: Justin S. Legakis, Franklin C. Crow, John S. Montrym, Douglas A. Voorhies
  • Patent number: 7171051
    Abstract: Method and apparatus for providing texture and/or alpha compression. In one embodiment, the present invention incorporates stored palettes, e.g., a luminance palette and a chrominance palette such that, compressed texture data pertaining to a fixed blocksize is decoded and applied to the stored palettes to extract the texel data. In a second embodiment, the present method uses a plane to estimate the alpha value at each of the texels, and a three-bit correction factor to adjust the estimate to produce a final alpha value.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: January 30, 2007
    Assignee: Nvidia Corporation
    Inventors: Henry P. Moreton, Justin S. Legakis