Patents by Inventor Jw-Wang Hsu

Jw-Wang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple etch method for fabricating spacer layers
    Patent number: 6764911
    Abstract: Within a method for forming a spacer layer from a second layer formed of a second material laminated upon a first layer formed of a first material, in turn formed over a topographic feature, there is employed a three step etch method. The three step etch method employs: (1) a first etch method having a first enhanced etch selectivity for the second material with respect to the first material; (2) a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material; and (3) a third etch method having a third enhanced etch selectivity for the first material with respect to the second material. In accord with the three step etch method, the spacer layer is fabricated with enhanced dimensional control.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: July 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jw-Wang Hsu, Ming-Huan Tsai, Mei-Ru Kuo, Baw-Ching Peng, Hun-Jan Tao
  • Multiple etch method for fabricating spacer layers
    Publication number: 20030211697
    Abstract: Within a method for forming a spacer layer from a second layer formed of a second material laminated upon a first layer formed of a first material, in turn formed over a topographic feature, there is employed a three step etch method. The three step etch method employs: (1) a first etch method having a first enhanced etch selectivity for the second material with respect to the first material; (2) a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material; and (3) a third etch method having a third enhanced etch selectivity for the first material with respect to the second material. In accord with the three step etch method, the spacer layer is fabricated with enhanced dimensional control.
    Type: Application
    Filed: May 10, 2002
    Publication date: November 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jw-Wang Hsu, Ming-Huan Tsai, Mei-Ru Kuo, Baw-Ching Peng, Hun-Jan Tao