Abstract: A data storage element (10) comprises a switch (11) and a ferroelectric capacitor (12). The switch (11) has a control terminal connected to a word line (13), a first current conducting terminal coupled to a bit line (16) via the ferroelectric capacitor (12), and a second current conducting terminal connected to a plate line (14). The data storage element (10) fully restores data in the ferroelectric capacitor (12) after a reading operation without consuming extra power to boost the word line (13) voltage.

Abstract: A ferro-electric memory array (41) having a reduced size and increased performance is disclosed herein. The ferro-electric memory array (41) is arrayed in memory cell columns and memory cell rows. Each memory cell column shares a BIT or BITBAR line with an adjacent memory cell column. Two row enable lines are provided to each memory cell row. The row enable lines alternately couple to memory cells of a memory cell row to prevent a contention condition. Sharing BIT and BITBAR lines with adjacent memory cell columns reduces a width of the ferro-electric memory array (41) which reduces the resistance on each line CP for a memory cell row. The result is a memory array that is capable of operating at higher speeds. Also, using more than one row enable line in each row reduces the number of memory cells accessed in a read or write operation. This increases the endurance of the ferro-electric memory array (41) by a factor of two.

Abstract: The present invention provides a non-volatile register (10) and a method for writing data into and reading data from the non-volatile register (10). When writing, a first pair of ferroelectric capacitors (14, 16) receives a data signal via a first pass gate (12) and a second pair of ferroelectric capacitors (24, 26) receives a complementary data signal via a second pass gate (32). An extraction signal and a restoration signal place the two pairs of ferroelectric capacitors (14, 16, 24, 26) into their respective polarization states depending on the data. When reading, the extraction signal produces a voltage difference in accordance with the data stored in the register (10) appearing at two voltage electrodes of a voltage detector (18). The voltage difference is amplified and transmitted from the register (10) via the two pass gates (12, 32). The restoration signal restores the data back to the non-volatile register (10).

Abstract: A method for reading and restoring data in a FERAM (10) is provided. The FERAM (10) comprises a FET (11) and a ferroelectric capacitor (12). The FET (11) has a gate connected to a word line (14), a source coupled to a plate line (15) via the ferroelectric capacitor (12), and a drain connected to a bit line (16). The reading process begins by placing a predetermined amount of charge in a bit line capacitor (17), which in turn charges the ferroelectric capacitor (12) after the FET (11) is switched on, resulting in a voltage drop determined by data stored in the FERAM (10) at the bit line (16). A sense amplifier (18) adjusts the voltage at the bit line (16) accordingly to read data from the FERAM (10). Applying a voltage at the plate line (15) and switching the FET (11) off restore the data to the FERAM (10).

Abstract: A non-volatile RAM circuit (10) uses ferro-electric capacitors (14, 16) to store data in a dormant state. Data is initially stored on the ferro-electric capacitors. The data stored on the ferro-electric capacitors is transferred to a memory cell (25) when the RAM circuit is powered up. Subsequent read operations after the power-up sequence obtain data from the memory cell instead of the ferro-electric capacitors. Any write operation during the power-up sequence is stored in the memory cell. When power is removed, the ferro-electric capacitors are updated with the present state of the memory cell. The endurance and data retention time of the ferro-electic capacitors increases by accessing data from the memory cell.