Patents by Inventor Jy-Jie Gau

Jy-Jie Gau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11355406
    Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau, Jing-Cheng Lin
  • Publication number: 20200303275
    Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau, Jing-Cheng Lin
  • Patent number: 10699981
    Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau, Jing-Cheng Lin
  • Publication number: 20190067146
    Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Inventors: Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau, Jing-Cheng Lin
  • Patent number: 10115647
    Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 30, 2018
    Inventors: Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau, Jing-Cheng Lin
  • Publication number: 20160276248
    Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau, Jing-Cheng Lin
  • Patent number: 9343419
    Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The lateral dimension of the first metal pillar is greater than the lateral dimension of the second metal pillar.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Meng-Liang Lin, Jy-Jie Gau, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu
  • Publication number: 20140167254
    Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The lateral dimension of the first metal pillar is greater than the lateral dimension of the second metal pillar.
    Type: Application
    Filed: March 6, 2013
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Meng-Liang Lin, Jy-Jie Gau, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu
  • Patent number: 7005236
    Abstract: Maintaining photoresist thickness and uniformity over a substrate that includes various cavities presents problems, such as preventing distortion of features in the resist image close to cavity edges. These problems have been overcome by laying down the photoresist as two separate layers. The first layer is used to eliminate or reduce problems associated with the presence of the cavities. The second layer is processed in the normal way and does not introduce distortions close to a cavity's edge. A first embodiment introduces some liquid into the cavity before laying down the first layer while the second embodiment etches away part of the first layer before applying the second one. Application of the process to the formation of a cantilever that overhangs a cavity is also described.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: February 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Su-Jen Cheng, Bor-Ping Jang, Chun-Chieh Wang, Jy-Jie Gau
  • Publication number: 20040214112
    Abstract: Maintaining photoresist thickness and uniformity over a substrate that includes various cavities presents problems, such as preventing distortion of features in the resist image close to cavity edges. These problems have been overcome by laying down the photoresist as two separate layers. The first layer is used to eliminate or reduce problems associated with the presence of the cavities. The second layer is processed in the normal way and does not introduce distortions close to a cavity's edge. A first embodiment introduces some liquid into the cavity before laying down the first layer while the second embodiment etches away part of the first layer before applying the second one. Application of the process to the formation of a cantilever that overhangs a cavity is also described.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 28, 2004
    Applicant: Taiwan Semicondutor Manufacturing Co.
    Inventors: Su-Jen Cheng, Bor-Ping Jang, Chun-Chieh Wang, Jy-Jie Gau