Patents by Inventor Jye-Yen Cheng

Jye-Yen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10361156
    Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheung-Hsuan Wei, Li-Yu Lee, Tai-Yang Wu
  • Publication number: 20190157204
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 23, 2019
    Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, TaiYang WU
  • Publication number: 20190157139
    Abstract: An interconnect structure includes a damascene structure, an inter-metal dielectric (IMD), a dielectric block and a metal via. The inter-metal dielectric layer is over the damascene structure. The dielectric block is embedded in the IMD layer and has a different etch selectivity than the IMD layer. The metal via is in the IMD layer and through the dielectric block to electrically connect the damascene structure.
    Type: Application
    Filed: February 8, 2018
    Publication date: May 23, 2019
    Inventors: Jye-Yen CHENG, Chen-Yu SHYU, Ming-Shuoh LIANG
  • Publication number: 20190139815
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Yi-Chun HUANG, Chih-Hsiang YAO, Jye-Yen CHENG
  • Patent number: 10170355
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chun Huang, Chih-Hsiang Yao, Jye-Yen Cheng
  • Patent number: 10157843
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, TaiYang Wu
  • Patent number: 10102972
    Abstract: A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chun Hua, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao, Jye-Yen Cheng, Hua-Chou Tseng
  • Patent number: 10068836
    Abstract: An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Ho, Chih-Ping Chao, Hua-Chou Tseng, Chun-Hung Chen, Chia-Yi Su, Alex Kalnitsky, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • Publication number: 20180150581
    Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.
    Type: Application
    Filed: January 26, 2018
    Publication date: May 31, 2018
    Inventors: Shien-Yang Wu, Jye-Yen Cheng, Wei-Chang Kung
  • Publication number: 20180122738
    Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 3, 2018
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheung-Hsuan Wei, Li Yu Lee, Tai-Yang Wu
  • Publication number: 20180076141
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 15, 2018
    Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, TaiYang WU
  • Patent number: 9892221
    Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Jye-Yen Cheng, Wei-Chan Kung
  • Patent number: 9881870
    Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Pei-Ru Lee, Tai-Yang Wu
  • Patent number: 9852992
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, TaiYang Wu
  • Publication number: 20170316975
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature. A bottom surface of the second conductive feature is between a top surface of the first conductive feature and a bottom surface of the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. The semiconductor device also includes an etch stop layer between the first dielectric layer and the second dielectric layer. A top surface of the etch stop layer is between the top surface and the bottom surface of the first conductive feature.
    Type: Application
    Filed: July 13, 2017
    Publication date: November 2, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Chia-Tien WU, Jye-Yen CHENG
  • Patent number: 9793212
    Abstract: An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Chih-Hsiang Yao, Jye-Yen Cheng, Wen-Chuan Chiang, Ying-Wen Huang
  • Publication number: 20170271198
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.
    Type: Application
    Filed: June 7, 2017
    Publication date: September 21, 2017
    Inventors: Yi-Chun HUANG, Chih-Hsiang YAO, Jye-Yen CHENG
  • Publication number: 20170221827
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.
    Type: Application
    Filed: April 11, 2017
    Publication date: August 3, 2017
    Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, TaiYang WU
  • Patent number: 9721836
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature, and the second conductive feature extends into the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. The semiconductor device also includes an etch stop layer between the first dielectric layer and the second dielectric layer. The etch stop layer surrounds the first conductive feature, and a bottom surface of the second conductive feature is above the etch stop layer.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chia-Tien Wu, Jye-Yen Cheng
  • Publication number: 20170213780
    Abstract: An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 27, 2017
    Inventors: Chien-Chih HO, Chih-Ping CHAO, Hua-Chou TSENG, Chun-Hung CHEN, Chia-Yi SU, Alex KALNITSKY, Jye-Yen CHENG, Harry-Hak-Lay CHUANG