Abstract: A method by which the gate oxide in an EEPROM device is selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior during programming of a selected cell. First the lattice structure in a portion of the channel near said drain region is intentionally damaged to enhance subsequent thermal oxidation therein. Next, the channel is thermally oxidized to form the tunnel oxide for the device. Due to the damage inflicted in the portion of the channel near the drain, the tunnel oxide over the damaged region is thicker relative to the other portion of the channel. A thicker gate oxide near the drain thwarts drain disturbance in adjacent memory cells while speeding up source erase performance.

Abstract: An electrically programmable memory array including a plurality of memory cells for storing data aligned in rows and columns, a plurality of word lines each connected to the gate terminals of the memory cells in a particular row, a plurality of bit lines each connected to the drain terminals of the memory cells aligned in a particular column, and a plurality of source conductors each electrically connected only to the source terminals of the memory cells in a particular row. This architecture lends itself to a finer granularity of small blocks without extra memory cell area.

Abstract: A three-dimensional contactless non-volatile memory cell is described. The memory cell comprises a substrate, source/drain regions that function as buried bit-lines and define a channel therebetween, a floating gate disposed above and insulated from the channel, and a control gate disposed above and insulated from the floating gate. The floating gate is formed to an adequate thickness so as to allow capacitive coupling to the control gate along the vertical regions of the floating gate. Thus, a reduction in minimum cell size can be achieved by decreasing the lateral dimensions of the cell without compromising the total capacitive coupling area. Subsequently, a substantial reduction in the total array area and a corresponding increase in device density can be realized. Further features of the invention include elimination of thick oxide regions in the array and improved gate oxide quality.

Abstract: A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the source and drain has both horizontal and vertical regions. The cell also includes a floating gate, which is completely surrounded with insulation, and a control gate which is insulated above and extends over the floating gate. The control gate is also insulated above and extends over the vertical portion of the channel within the slot. This allows the second gate member to regulate the current flowing in the vertical portion of the channel; that is, the second gate member and the vertical channel section form an integral select device.

Abstract: A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the source and drain has both horizontal and vertical regions. The cell also includes a floating gate, which is completely surrounded with insulation, and a control gate which is insulated above and extends over the floating gate. The control gate is also insulated above and extends over the vertical portion of the channel within the slot. This allows the second gate member to regulate the current flowing in the vertical portion of the channel; that is, the second gate member and the vertical channel section form an integral select device.