Patents by Inventor Jyh-Cherng Yau
Jyh-Cherng Yau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8282842Abstract: A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.Type: GrantFiled: November 29, 2007Date of Patent: October 9, 2012Assignee: United Microelectronics Corp.Inventors: Chieh-Ju Wang, Jyh-Cherng Yau, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Patent number: 8137472Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.Type: GrantFiled: June 16, 2011Date of Patent: March 20, 2012Assignee: United Microelectronics Corp.Inventors: Chang-Hsiao Lee, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20120061840Abstract: A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.Type: ApplicationFiled: November 17, 2011Publication date: March 15, 2012Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Patent number: 8101092Abstract: A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.Type: GrantFiled: October 24, 2007Date of Patent: January 24, 2012Assignee: United Microelectronics Corp.Inventors: Chih-Wen Feng, Pei-Yu Chou, Chun-Ting Yeh, Jyh-Cherng Yau, Jiunn-Hsiung Liao, Feng-Yi Chang, Ying-Chih Lin
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Patent number: 8080877Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: GrantFiled: June 23, 2010Date of Patent: December 20, 2011Assignee: United Microelectronics Corp.Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20110244678Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chang-Hsiao LEE, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Patent number: 7977244Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.Type: GrantFiled: December 18, 2006Date of Patent: July 12, 2011Assignee: United Microelectronics Corp.Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20110130008Abstract: A method to control a critical dimension is disclosed. First, a material layer and a composite patterned layer covering the material layer are provided. The composite patterned layer has a pattern defining a first critical dimension. Later, an etching gas is used to perform an etching step to etch the composite patterned layer and a pattern-transferring step is carried out so that thereby the underlying material layer has a transferred pattern with a second critical dimension which is substantially smaller than the first critical dimension.Type: ApplicationFiled: December 1, 2009Publication date: June 2, 2011Inventors: Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20100258941Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Patent number: 7767578Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: GrantFiled: January 11, 2007Date of Patent: August 3, 2010Assignee: United Microelectronics Corp.Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20100105205Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.Type: ApplicationFiled: October 27, 2008Publication date: April 29, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chang-Hsiao Lee, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20100018944Abstract: A patterning method is provided. A patterned photoresist layer is formed on a bottom anti-reflective coating (BARC), having therein an opening exposing a portion of the BARC. The patterned photoresist layer is treated with a first plasma-generating gas including a fluorocarbon species to form a polymer layer on the surface of the PR layer and the sidewall of the opening. The patterned photoresist layer is used as a mask to etch the BARC with a second plasma-generating gas, which includes Ar and H2 but no fluorocarbon species or oxygen-containing species, to remove the exposed portion of the BARC.Type: ApplicationFiled: July 25, 2008Publication date: January 28, 2010Applicant: United Microelectronics Corp.Inventors: Yu-Tsung Lai, Shih-Chang Chang, Chieh-Ju Wang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20090142931Abstract: A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Inventors: Chieh-Ju Wang, Jyh-Cherng Yau, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Publication number: 20090107954Abstract: A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.Type: ApplicationFiled: October 24, 2007Publication date: April 30, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: CHIH-WEN FENG, PEI-YU CHOU, CHUN-TING YEH, JYH-CHERNG YAU, JIUNN-HSIUNG LIAO, FENG-YI CHANG, YING-CHIH LIN
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Publication number: 20080171433Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20080146036Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.Type: ApplicationFiled: December 18, 2006Publication date: June 19, 2008Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao