Abstract: A fabrication method for forming asymmetric wells of a DRAM cell, and more particularly to a fabrication method for producing a transistor that is capable of reducing body effect, gate-swing and junction leakage current so as to enhance the reliability of a DRAM device. After doped regions used for source/drain are formed in a substrate, a local well and an anti-punchthrough pocket are then formed under the doped region to be used as drains in order to prevent short channel effect. Because the local well and the anti-punchthrough pocket do not extend to the doped region that is used as a source, the DRAM cell's ability for charge retention therefore can be kept at the same time.

Abstract: A method of forming asymmetric source/drain for a DRAM cell, whereas a graded junction is formed at a node contact terminal and an abrupt junction being formed at a bit line contact terminal, so as to reduce the short channel effect in the bit line contact region and junction leakage current at the contact node, both of a DRAM cell, so that the charge retention time is augmented.