Abstract: An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.

Abstract: An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.

Abstract: An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region.

Abstract: A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.

Abstract: The present invention is directed to a device and method for generating a reference voltage. A reference voltage generator comprises a first circuit, a second circuit, and an external device. The first circuit generates a positive temperature coefficient voltage. the second circuit is coupled to the first circuit, biased with a substantially constant current, produces a negative temperature coefficient voltage, and combines the negative temperature coefficient voltage with the positive temperature coefficient voltage as a reference voltage. The external device is coupled to the second circuit, and yields the substantially constant current.

Abstract: A multimode communications system includes a first communications module, a transmission module, a switch and a second communications module. The first communication module has a frequency modulator for modulating a dividing ratio to adjust an oscillating signal and selectively enabling the oscillating signal to have its frequency change with a variety of contents of a first communications signal by modulating the dividing ratio according to the contents of the first communications signal on a modulating mode or enabling the oscillating signal to have its frequency constant by keeping the dividing ratio unchanged. The switch is to selectively transmit the oscillating signal either to the transmission module when the frequency modulator is operating on the modulating mode or to a receiving end when the frequency modulator is operating on the constant frequency mode.

Abstract: A wireless communication device. The wireless communication device comprises first and second programmable frequency dividers, a mixer, a modulator, a phase detector, and a variable controlled oscillator. The first programmable frequency divider divides the frequency of a reference signal by a factor N to generate a modulating signal. The second programmable frequency divider divides the reference signal by a factor M and outputs a frequency-divided signal. The facts N and M are positive integers. The mixer down-converting a transmission signal according the divided signal and outputs a translation-loop signal. The modulator modulates the modulating signal with baseband signals, and outputs a comparison signal. The phase detector detects a phase difference between the comparison signal and the translation-loop signal. The variable controlled oscillator modifies the transmission signals according to an output of the phase detector.

Abstract: A signal compensation circuit and associated method dynamically compensate for signal baseline wandering in a transmission line. The compensation circuit has a detection circuit and a correction circuit. The detection circuit first compares a transmission signal with a reference level and generates a comparison result. The correction circuit then corrects the transmission signal according to the comparison result. The compensation circuit can adjust its compensation over time based on the quality of the transmission signal.

Abstract: The present invention is directed to a device and method for generating a reference voltage. A reference voltage generator comprises a first circuit, a second circuit, and an external device. The first circuit generates a positive temperature coefficient voltage. the second circuit is coupled to the first circuit, biased with a substantially constant current, produces a negative temperature coefficient voltage, and combines the negative temperature coefficient voltage with the positive temperature coefficient voltage as a reference voltage. The external device is coupled to the second circuit, and yields the substantially constant current.

Abstract: A clock recovery circuit for generating an output signal that is synchronized with an input signal. The clock recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.

Abstract: A high-speed, low-noise charge pump for use in a phase-locked loop. The charge pump is constituted by first and second cascode current mirrors, as well as first and second switching transistors. The first cascode current mirror includes a first output mirror transistor and a first output cascode transistor. The first switching transistor is interposed between the first output mirror and the first output cascode transistors. During assertion of a first control signal, the first switching transistor is turned on so a first mirror current can flow through an output node. Likewise, the second cascode current mirror includes a second output mirror transistor and a second output cascode transistor. The second switching transistor is interposed between the second output mirror and the second output cascode transistors. During assertion of a second control signal, the second switching transistor is turned on so the second mirror current can flow through the output node.

Abstract: A frequency divider for dividing a frequency of a clock signal by an odd divisor includes a flip-flop chain for latching signals having a number of flip-flops equal to the divisor. The frequency divider also has an XOR gate having two input nodes and an output node, one input node being electrically connected to the clock signal, the other input node being electrically connected to an inverted output node of the last flip-flop, and the output node of the XOR gate being electrically connected to clock input nodes of the odd flip-flops in the flip-flop chain. The frequency divider further has an inverter, an input node of the inverter being electrically connected to the output node of the XOR gate, an output node of the inverter being electrically connected to clock input nodes of the even flip-flops in the flip-flop chain.

Abstract: A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.

Abstract: A hysteresis comparing device with constant hysteresis width and the method thereof, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: A multimode communications system includes a first communications module, a transmission module, a switch and a second communications module. The first communication module has a frequency modulator for modulating a dividing ratio to adjust an oscillating signal and selectively enabling the oscillating signal to have its frequency change with a variety of contents of a first communications signal by modulating the dividing ratio according to the contents of the first communications signal on a modulating mode or enabling the oscillating signal to have its frequency constant by keeping the dividing ratio unchanged. The switch is to selectively transmit the oscillating signal either to the transmission module when the frequency modulator is operating on the modulating mode or to a receiving end when the frequency modulator is operating on the constant frequency mode.

Abstract: A high-speed, low-noise charge pump for use in a phase-locked loop. The charge pump is constituted by first and second cascode current mirrors, as well as first and second switching transistors. The first cascode current mirror includes a first output mirror transistor and a first output cascode transistor. The first switching transistor is interposed between the first output mirror and the first output cascode transistors. During assertion of a first control signal, the first switching transistor is turned on so a first mirror current can flow through an output node. Likewise, the second cascode current mirror includes a second output mirror transistor and a second output cascode transistor. The second switching transistor is interposed between the second output mirror and the second output cascode transistors. During assertion of a second control signal, the second switching transistor is turned on so the second mirror current can flow through the output node.

Abstract: An analog-to-digital data converter converts an input signal to corresponding digital signals. The data converter includes two sets of comparison units arranged in an interlaced sense to alternatively analyze the input signal, generate digital signals corresponding to the result of comparing the input signal and reference signals. Each of the comparison units has a positive output and a negative output, and the digital signal is generated by the negative output and the positive output of the comparison units in a differential way. When the comparison units of one set are performing auto-zeroing, the comparison units of the other set perform the data conversion to generate corresponding digital signals.

Abstract: A frequency divider for dividing a frequency of a clock signal by an odd divisor includes a flip-flop chain for latching signals having a number of flip-flops equal to the divisor. The frequency divider also has an XOR gate having two input nodes and an output node, one input node being electrically connected to the clock signal, the other input node being electrically connected to an inverted output node of the last flip-flop, and the output node of the XOR gate being electrically connected to clock input nodes of the odd flip-flops in the flip-flop chain. The frequency divider further has an inverter, an input node of the inverter being electrically connected to the output node of the XOR gate, an output node of the inverter being electrically connected to clock input nodes of the even flip-flops in the flip-flop chain.

Abstract: An analog-to-digital data converter converts an input signal to corresponding digital signals. The data converter includes two sets of comparison units arranged in an interlaced sense to alternatively analyze the input signal, generate digital signals corresponding to the result of comparing the input signal and reference signals. Each of the comparison units has a positive output and a negative output, and the digital signal is generated by the negative output and the positive output of the comparison units in a differential way. When the comparison units of one set are performing auto-zeroing, the comparison units of the other set perform the data conversion to generate corresponding digital signals.

Abstract: A hysteresis comparing device with constant hysteresis width, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.