Abstract: A method for preventing gate oxide damage caused by post poly definition implantation is disclosed. It is shown that the antenna ratio that is correlatable to oxide damage can be reduced and made to approach zero by implementing a mask layout during ion implantation. This involves covering all of the polysilicon electrodes with a photoresist mask, and reducing the effective antenna ratio to zero, and performing ion implantation to form source/drain regions thereafter. In this manner, the dependency of ion implantation to pattern sensitivity is also removed.

Abstract: A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Abstract: A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.

Abstract: The invention provides a method for fabricating ultra-shallow lightly doped source and drain regions. A screen oxide layer is formed on a substrate having a gate thereon. Impurity ions are implanted into-the substrate through the screen oxide layer to form lightly doped source and drain regions adjacent to the gate. A post-implant anneal is performed on the lightly doped source and drain regions using a rapid thermal anneal in a nitrogen containing atmosphere. The nitrogen anneal injects vacancies into the lightly doped source and drain regions reducing diffusion which is dependent on intersticial ions and increasing the activation ratio by dissolving impurity ion complexes.

Abstract: The invention provides a method for fabricating ultra-shallow, low resistance junctions. In the preferred embodiment, a nitrogen containing screen oxide layer is formed on an undoped area of a substrate by poly re-oxidation using rapid thermal processing in a nitrogen containing atmosphere. Impurity ions are implanted into the substrate, in the undoped area, through the nitrogen containing screen oxide layer to form lightly doped source and drain regions. A post-implant anneal is performed on the lightly doped source and drain regions using a rapid thermal anneal in a nitrogen containing atmosphere. The nitrogen containing screen oxide layer: prevents surface dopant loss during post implant anneal; prevents gate oxide degradation during ion implantation and screen oxide stripping; and acts as a diffusion barrier, reducing oxygen enhanced diffusion. Alternatively, the poly re-oxidation can be performed in an O2 atmosphere followed by a rapid thermal anneal in a nitrogen containing atmosphere.

Abstract: A method for preventing gate oxide damage caused by post poly definition implantation is disclosed. It is shown that the antenna ratio that is correlatable to oxide damage can be reduced and made to approach zero by implementing a mask layout during ion implantation. This involves covering all of the polysilicon electrodes with a photoresist mask, and reducing the effective antenna ratio to zero, and performing ion implantation to form source/drain regions thereafter. In this manner, the dependency of ion implantation to pattern sensitivity is also removed.

Abstract: A process for fabricating a core device, featuring an LDD source/drain region, with a sharp dopant profile, while simultaneously fabricating an I/O device, featuring an LDD source/drain region, with a graded dopant profile, has been developed. The process features the initial creation of the core device, LDD source/drain region, via an ion implantation, and RTA procedure, resulting in an LDD region with a sharp dopant profile, needed for enhanced performance. The I/O device, LDD source/drain region, is next addressed via an ion implantation procedure, followed by the creation of insulator spacers, formed at a temperature that TED occurs, to allow a graded dopant profile to be achieved for the I/O device, source/drain region, thus reducing hot carrier reliability risks.

Abstract: A process for fabricating an I/O device, comprised with an LDD source/drain region, featuring a graded dopant profile, and simultaneously fabricating a core device, comprised with an LDD source/drain region, featuring a sharp dopant profile, has been developed. The process features the initial creation of the I/O device, LDD source/drain region, via an ion implantation procedure, followed by a furnace anneal procedure, to initiate transient enhanced diffusion, resulting in a graded dopant profile, for the I/O device, LDD source/drain region. The graded dopant profile, affords reduced risk of hot carrier effects, prevalent with the higher voltage, I/O devices. The creation of the core device, LDD source/drain region, is next addressed via another ion implantation, followed by a RTA procedure, used to activate the implanted species, and to create an LDD source/drain region, for the core device, featuring a sharp dopant profile, needed for performance objectives.

Abstract: A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that creates an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

Abstract: A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that created an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.