Abstract: A clock generation device comprises a clock generation unit, a counter, a common factor calculation element, a first frequency divider, a phase-locked loop (PLL) and a second frequency divider. The counter receives a clock signal from the clock generation unit and a periodic signal from a USB host, and outputs a count value. The common factor calculation element calculates the common factor of the count value and a value to output a first adjustment value and a second adjustment value. The first frequency divider divides the frequency of the clock signal by the first adjustment value to output a reference signal. The second frequency divider divides the frequency of the output clock signal of the PLL by the second adjustment value to obtain a feedback signal input to the PLL. Based on the reference signal and the feedback signal, the PLL outputs a clock signal complying with the USB specification.

Abstract: A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes.

Abstract: A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes.

Abstract: The present invention provides a data-read/write method of a bridge interface, which via appropriately controlling the signal level and the timing between the host system and the device, enables the bridge interface to have a complete information handshake, so that the bridge interface can work at any transferring speed and easily transform any instruction stream coming from a front bus. Accordingly, the present invention has the advantages of high compatibility and easiness of transforming instruction streams.

Abstract: The present invention discloses a wave reduction sampling method of signal output. The method includes smoothing the original digital signal at a host terminal to rebuild a simulating signal, and sampling the simulating signal with a sampling rate to obtain a reductive signal. The sampling rate is an operating frequency of an audio/image outputting apparatus divided by a transmission multiple value. The claimed invention transfers the sampling rate by software at the host terminal to reduce the signal to output, and has advantages of having flexible outputting frequency, being suitable to any operating frequency, omitting the clock synthesizer and reducing the cost.

Abstract: A system implement simulation system's capable of facilitating integrated circuit designers to perform a complete integrated circuit testing with respect to a target peripheral device and demonstrate various functions and their sequence of operations without having to build the target device physically. The system allows, reliability and quality of an integrated circuit design to be increased, and production and testing costs can be reduced. The simulation system is capable of performing functional checking at any time, and can be utilized in demonstrating product functions to customer.