Patents by Inventor Jyh-Nan Lin
Jyh-Nan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967522Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: April 25, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20230377955Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen CHEN, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 11742393Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: GrantFiled: March 1, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
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Publication number: 20220262677Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Hsiao-Min CHEN, Jyh-Nan LIN, Kai-Shiung HSU, Ding-I LIU
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Publication number: 20220254679Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20220190122Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: ApplicationFiled: March 1, 2022Publication date: June 16, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan LIN, Ding-I Liu, Yuh-Ta Fan
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Publication number: 20220181203Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen Chen, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 11322397Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: GrantFiled: October 25, 2019Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiao-Min Chen, Jyh-Nan Lin, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 11315829Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: June 2, 2020Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 11264273Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: GrantFiled: July 28, 2020Date of Patent: March 1, 2022Inventors: Chun-Jen Chen, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 11264467Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: GrantFiled: August 5, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
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Publication number: 20210233805Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: July 28, 2020Publication date: July 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen CHEN, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 10978337Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.Type: GrantFiled: August 26, 2019Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jyh-nan Lin, Mu-Min Hung, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20210066122Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the n etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: ApplicationFiled: June 2, 2020Publication date: March 4, 2021Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20200365695Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: ApplicationFiled: August 5, 2020Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
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Patent number: 10749004Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: GrantFiled: June 15, 2018Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
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Publication number: 20200135553Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: ApplicationFiled: October 25, 2019Publication date: April 30, 2020Inventors: Hsiao-Min CHEN, Jyh-Nan LIN, Kai-Shiung HSU, Ding-I LIU
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Patent number: 10373906Abstract: Structures and formation methods of a semiconductor device structure are provided. A method includes depositing a first layer including Al atoms to cover a first dielectric layer in a first conductive feature. The method also includes depositing a second layer including N atoms over the first layer. The first layer and the second layer form an etch stop layer including aluminum nitride. The etch stop layer includes vacancies and has an atomic percentage of Al to Al and N. The method also includes filling the vacancies in the etch stop layer with additional N atoms to reduce the atomic percentage of Al to Al and N. In addition, the method includes forming a second dielectric layer over the etch stop layer. The method also includes forming a second conductive feature in the second dielectric layer and the etch stop layer to be connected to the first conductive feature.Type: GrantFiled: April 20, 2017Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jyh-Nan Lin, Tsung-Dar Lee, Li Chen
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Publication number: 20190006474Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: ApplicationFiled: June 15, 2018Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
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Publication number: 20180308793Abstract: Structures and formation methods of a semiconductor device structure are provided. A method includes depositing a first layer including Al atoms to cover a first dielectric layer in a first conductive feature. The method also includes depositing a second layer including N atoms over the first layer. The first layer and the second layer form an etch stop layer including aluminum nitride. The etch stop layer includes vacancies and has an atomic percentage of Al to Al and N. The method also includes filling the vacancies in the etch stop layer with additional N atoms to reduce the atomic percentage of Al to Al and N. In addition, the method includes forming a second dielectric layer over the etch stop layer. The method also includes forming a second conductive feature in the second dielectric layer and the etch stop layer to be connected to the first conductive feature.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan LIN, Tsung-Dar LEE, Li CHEN