Abstract: A self-aligned fabricating process and a structure of ETOX flash memory. A plurality of parallel lines for device isolation is formed in a substrate, and then forming a plurality of parallel stacked gates above the substrate. The device isolation lines and the stacked gates are perpendicular to each other. A plurality of first insulation layers is formed such that an insulation layer is formed over each stacked gate. Spacers are also formed over the sidewalls of each stacked gate. A plurality of source arrays and drain arrays are formed in the substrate between neighboring stacked gates. The source and drain arrays are parallel to the stacked gates, with a source array and a drain array formed in alternating positions between the stacked gates. Each source array comprises a plurality of source-doped regions located between the device isolation lines respectively. Similarly, each drain array has a plurality of drain-doped regions located between the device isolation lines.

Abstract: A method is used to form a borderless via in a semiconductor device. A conductive layer, a borophosphosilicate glass (BPSG) layer and a patterned first mask layer are formed on a dielectric layer in sequence. The BPSG layer is patterned into a BPSG plug while using the patterned first mask layer as a mask. A second mask layer is formed to cover the patterned first mask layer and the metal layer. The conductive layer is defined to form a conductive line beneath the BPSG plug and the second mask layer. The first and second photoresist mask layers are removed. An inter-metal dielectric layer is formed around the BPSG plug and the conductive line. A via is formed in the inter-metal dielectric layer by removing the BPSG plug. A barrier layer and a metal layer fill the via to form a metal plug.

Abstract: A bonding pad structure and its method of manufacture. The structure has a metallic bonding pad with a patterned surface, a first passivation layer having an opening above the metallic bonding pad and a second passivation layer over the first passivation layer also having an opening above the metallic bonding pad. The method of forming the bonding pad structure includes forming a metallic bonding pad over a substrate, and then forming a first passivation layer over the substrate and the bonding pad. The first passivation layer above the bonding pad is patterned. Using the first passivation layer as a mask, a portion of the exposed metal pad material is removed. A patterned second passivation layer is formed over the first passivation layer. The second passivation layer has an opening that exposes the bonding pad. Finally, residual material from the first passivation layer inside the bonding pad region is removed to expose the bonding pad surface.

Abstract: A method for fabricating a borderless via on a semiconductor device is described in which a substrate comprising a dielectric layer is provided. A conductive layer, a barrier layer and a metal layer are sequentially formed on the dielectric layer. A first photoresist pattern is further formed to cover the metal layer. A first etching step is then conducted using the barrier layer as an etching end point and the photoresist pattern as an etching mask. The tungsten metal layer is etched to form a tungsten metal plug in the first etching step. Thereafter, a second photoresist pattern is formed on the barrier layer, partially covering the first photoresist pattern and the barrier layer. A second etching is then conducted on the barrier layer and the metal layer to form a conductive line, using the first photoresist pattern and the second photoresist pattern as etching masks. The first and the second photoresist patterns are then removed.

Abstract: A bonding pad is described. A substrate having integrated circuits formed therein is provided. A dielectric layer having several trench structure formed therein is formed over the substrate, and each trench structure has several trenches radially arranged in the dielectric layer. A conductive layer is formed on the dielectric layer and fills the trenches, and the conductive layer is electrically coupled to the integrated circuits in the substrate through the trenches, respectively. By using the invention, the adhesion of the dielectric layers and the metal layers can be greatly improved and the compressive mechanical stress can be uniformly released to the substrate even if the wire width of the integrated circuit is reduced to the sub-micron level.

Abstract: A method of manufacturing mask read-only-memory. The method includes forming a plurality of first and second active regions in designated locations on a substrate. Each first and second active region has a channel region and a source/drain region on both side of the channel. Subsequently, shallow trench oxide are formed within the channel regions of the first active regions, and then source/drain terminals are formed in the respective source/drain regions of first and second active regions. Finally, a gate terminal is formed over the channel region.

Abstract: The invention describes a method of fabricating an integrated circuit used to prevent undercutting of an oxide layer due to wet etching. A semiconductor substrate has a gate formed thereon. A conformal oxide layer is formed to cover the gate. Then, a nitrogen ion implantation process is performed to introduce nitrogen ions into the surface of the conformal oxide layer. A high temperature thermal oxidation is performed in order to form Si--N bonds, that is, the nitrogen ions bonding with the silicon atoms of the conformal oxide layer, or to form Si--ON bonds, that is, the nitrogen ions bonding with the oxygen atoms of the conformal oxide layer. A dielectric layer, which covers the conformal oxide layer, is formed. Thereafter, the dielectric layer is etched back to form spacers on the sidewalls of the gate. A wet etching process is performed to remove a part of the conformal oxide layer exposed by the spacers.